[RISCV] Use the extensions in the canonical order (NFC)

Use the ISA extensions for specific processors in the conventional canonical order.

diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 578b393..66eda3b 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -231,16 +231,16 @@ def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
 def : ProcessorModel<"bullet-rv32", BulletModel, []>;
 def : ProcessorModel<"bullet-rv64", BulletModel, [Feature64Bit]>;
 
-def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtA,
-                                                 FeatureStdExtC,
-                                                 FeatureStdExtM]>;
+def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
+                                                 FeatureStdExtA,
+                                                 FeatureStdExtC]>;
 
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
+                                                 FeatureStdExtM,
+                                                 FeatureStdExtF,
                                                  FeatureStdExtA,
-                                                 FeatureStdExtC,
                                                  FeatureStdExtD,
-                                                 FeatureStdExtF,
-                                                 FeatureStdExtM]>;
+                                                 FeatureStdExtC]>;
 
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.