arm64: dts: renesas: r9a09g011: Add L2 Cache node

The Cortex-A53 processor on RZ/V2M has 512 KB L2 Cache.
Add L2 Cache node to SoC dtsi.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221110160931.101539-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 2ccd48e..ca9f022 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -37,8 +37,15 @@
                        compatible = "arm,cortex-a53";
                        reg = <0>;
                        device_type = "cpu";
+                       next-level-cache = <&L2_CA53>;
                        clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
                };
+
+               L2_CA53: cache-controller-0 {
+                       compatible = "cache";
+                       cache-unified;
+                       cache-level = <2>;
+               };
        };
 
        soc: soc {