+2018-02-23 Carl Love <cel@us.ibm.com>
+
+ * config/rs6000/rs6000-builtin.def: Change VSIGNED2 and VUNSIGNED2
+ macro expansions from BU_VSX_2 to BU_P8V_VSX_2 and BU_VSX_OVERLOAD_2 to
+ BU_P8V_OVERLOAD_2.
+ * config/rs6000/rs6000-c.c: Change VSX_BUILTIN_VEC_VSIGNED2 to
+ P8V_BUILTIN_VEC_VSIGNED2. Change VSX_BUILTIN_VEC_VUNSIGNED2 to
+ P8V_BUILTIN_VEC_VUNSIGNED2.
+
2018-02-22 Vladimir Makarov <vmakarov@redhat.com>
PR target/81572
BU_VSX_2 (CMPLE_U4SI, "cmple_u4si", CONST, vector_ngtuv4si)
BU_VSX_2 (CMPLE_U2DI, "cmple_u2di", CONST, vector_ngtuv2di)
-BU_VSX_2 (VEC_VSIGNED2_V2DF, "vsigned2_v2df", CONST, vsigned2_v2df)
-BU_VSX_2 (VEC_VUNSIGNED2_V2DF, "vunsigned2_v2df", CONST, vunsigned2_v2df)
-
/* VSX abs builtin functions. */
BU_VSX_A (XVABSDP, "xvabsdp", CONST, absv2df2)
BU_VSX_A (XVNABSDP, "xvnabsdp", CONST, vsx_nabsv2df2)
BU_VSX_OVERLOAD_2 (XXMRGLW, "xxmrglw")
BU_VSX_OVERLOAD_2 (XXSPLTD, "xxspltd")
BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw")
-BU_VSX_OVERLOAD_2 (VSIGNED2, "vsigned2")
-BU_VSX_OVERLOAD_2 (VUNSIGNED2, "vunsigned2")
/* 1 argument VSX overloaded builtin functions. */
BU_VSX_OVERLOAD_1 (DOUBLE, "double")
BU_P8V_VSX_2 (FLOAT2_V2DF, "float2_v2df", CONST, float2_v2df)
BU_P8V_VSX_2 (FLOAT2_V2DI, "float2_v2di", CONST, float2_v2di)
BU_P8V_VSX_2 (UNS_FLOAT2_V2DI, "uns_float2_v2di", CONST, uns_float2_v2di)
+BU_P8V_VSX_2 (VEC_VSIGNED2_V2DF, "vsigned2_v2df", CONST, vsigned2_v2df)
+BU_P8V_VSX_2 (VEC_VUNSIGNED2_V2DF, "vunsigned2_v2df", CONST, vunsigned2_v2df)
+
/* 1 argument altivec instructions added in ISA 2.07. */
BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2)
BU_P8V_OVERLOAD_2 (VSUBUQM, "vsubuqm")
BU_P8V_OVERLOAD_2 (FLOAT2, "float2")
BU_P8V_OVERLOAD_2 (UNS_FLOAT2, "uns_float2")
+BU_P8V_OVERLOAD_2 (VSIGNED2, "vsigned2")
+BU_P8V_OVERLOAD_2 (VUNSIGNED2, "vunsigned2")
/* ISA 2.07 vector overloaded 3 argument functions. */
BU_P8V_OVERLOAD_3 (VADDECUQ, "vaddecuq")
RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
{ VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
- { VSX_BUILTIN_VEC_VSIGNED2, VSX_BUILTIN_VEC_VSIGNED2_V2DF,
+ { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF,
RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
{ VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
{ VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
- { VSX_BUILTIN_VEC_VUNSIGNED2, VSX_BUILTIN_VEC_VUNSIGNED2_V2DF,
+ { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
RS6000_BTI_V2DF, 0 },
+2018-02-23 Carl Love <cel@us.ibm.com>
+
+ * gcc.target/powerpc/builtins-3-runnable.c: Move tests for vec_float2,
+ vec_signed2 and vec_unsigned2 to new Power 8 test file.
+ * gcc.target/powerpc/builtins-3-runnable-p8.c: New test file for
+ Power 8 tests.
+
2018-02-23 Will Schmidt <will_schmidt@vnet.ibm.com>
* gcc.target/powerpc/pr80695-p9.c: Update dg-requires stanza.
--- /dev/null
+/* { dg-do run { target { powerpc*-*-linux* && { p8vector_hw } } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=power8" } } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h> // vector
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#define ALL 1
+#define EVEN 2
+#define ODD 3
+
+void abort (void);
+
+void test_int_result(int check, vector int vec_result, vector int vec_expected)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ switch (check) {
+ case ALL:
+ break;
+ case EVEN:
+ if (i%2 == 0)
+ break;
+ else
+ continue;
+ case ODD:
+ if (i%2 != 0)
+ break;
+ else
+ continue;
+ }
+
+ if (vec_result[i] != vec_expected[i]) {
+#ifdef DEBUG
+ printf("Test_int_result: ");
+ printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n",
+ i, vec_result[i], i, vec_expected[i]);
+#else
+ abort();
+#endif
+ }
+ }
+}
+
+void test_unsigned_int_result(int check, vector unsigned int vec_result,
+ vector unsigned int vec_expected)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ switch (check) {
+ case ALL:
+ break;
+ case EVEN:
+ if (i%2 == 0)
+ break;
+ else
+ continue;
+ case ODD:
+ if (i%2 != 0)
+ break;
+ else
+ continue;
+ }
+
+ if (vec_result[i] != vec_expected[i]) {
+#ifdef DEBUG
+ printf("Test_unsigned int_result: ");
+ printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n",
+ i, vec_result[i], i, vec_expected[i]);
+#else
+ abort();
+#endif
+ }
+
+ }
+}
+
+void test_result_sp(int check, vector float vec_result,
+ vector float vec_expected)
+{
+ int i;
+ for(i = 0; i<4; i++) {
+
+ switch (check) {
+ case ALL:
+ break;
+ case EVEN:
+ if (i%2 == 0)
+ break;
+ else
+ continue;
+ case ODD:
+ if (i%2 != 0)
+ break;
+ else
+ continue;
+ }
+
+ if (vec_result[i] != vec_expected[i]) {
+#ifdef DEBUG
+ printf("Test_result_sp: ");
+ printf("vec_result[%d] (%f) != vec_expected[%d] (%f)\n",
+ i, vec_result[i], i, vec_expected[i]);
+#else
+ abort();
+#endif
+ }
+ }
+}
+
+int main()
+{
+ int i;
+ vector unsigned int vec_unint, vec_uns_int_expected, vec_uns_int_result;
+ vector signed int vec_int, vec_int_expected, vec_int_result;
+ vector float vec_flt, vec_flt_result, vec_flt_expected;
+ vector long long int vec_ll_int0, vec_ll_int1;
+ vector long long unsigned int vec_ll_uns_int0, vec_ll_uns_int1;
+ vector double vec_dble0, vec_dble1, vec_dble_result, vec_dble_expected;
+
+ vec_ll_int0 = (vector long long int){ -12, -12345678901234 };
+ vec_ll_int1 = (vector long long int){ 12, 9876543210 };
+ vec_ll_uns_int0 = (vector unsigned long long int){ 102, 9753108642 };
+ vec_ll_uns_int1 = (vector unsigned long long int){ 23, 29 };
+
+ /* Convert two double precision vector float to vector int */
+ vec_dble0 = (vector double){-124.930, 81234.49};
+ vec_dble1 = (vector double){-24.370, 8354.99};
+ vec_int_expected = (vector signed int){-124, 81234, -24, 8354};
+ vec_int_result = vec_signed2 (vec_dble0, vec_dble1);
+ test_int_result (ALL, vec_int_result, vec_int_expected);
+
+ /* Convert two double precision vector float to vector unsigned int */
+ vec_dble0 = (vector double){124.930, 8134.49};
+ vec_dble1 = (vector double){24.370, 834.99};
+ vec_uns_int_expected = (vector unsigned int){124, 8134, 24, 834};
+ vec_uns_int_result = vec_unsigned2 (vec_dble0, vec_dble1);
+ test_unsigned_int_result (ALL, vec_uns_int_result,
+ vec_uns_int_expected);
+
+ /* conversion of two double precision vectors to single precision vector */
+ vec_flt_expected = (vector float){-12.00, -12345678901234.00, 12.00, 9876543210.00};
+ vec_flt_result = vec_float2 (vec_ll_int0, vec_ll_int1);
+ test_result_sp(ALL, vec_flt_result, vec_flt_expected);
+
+ vec_flt_expected = (vector float){102.00, 9753108642.00, 23.00, 29.00};
+ vec_flt_result = vec_float2 (vec_ll_uns_int0, vec_ll_uns_int1);
+ test_result_sp(ALL, vec_flt_result, vec_flt_expected);
+
+ vec_dble0 = (vector double){ 34.0, 97.0 };
+ vec_dble1 = (vector double){ 214.0, -5.5 };
+ vec_flt_expected = (vector float){34.0, 97.0, 214.0, -5.5};
+ vec_flt_result = vec_float2 (vec_dble0, vec_dble1);
+ test_result_sp(ALL, vec_flt_result, vec_flt_expected);
+}
+
-/* { dg-do run { target { p8vector_hw } } } */
+/* { dg-do run { target { vsx_hw } } } */
/* { dg-require-effective-target vsx_hw } */
-/* { dg-options "-O2 -mvsx -mcpu=power8" } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-maltivec -mvsx" } */
#include <altivec.h> // vector
vec_flt_result = vec_float (vec_unint);
test_result_sp(ALL, vec_flt_result, vec_flt_expected);
- /* conversion of two double precision vectors to single precision vector */
- vec_flt_expected = (vector float){-12.00, -12345678901234.00, 12.00, 9876543210.00};
- vec_flt_result = vec_float2 (vec_ll_int0, vec_ll_int1);
- test_result_sp(ALL, vec_flt_result, vec_flt_expected);
-
- vec_flt_expected = (vector float){102.00, 9753108642.00, 23.00, 29.00};
- vec_flt_result = vec_float2 (vec_ll_uns_int0, vec_ll_uns_int1);
- test_result_sp(ALL, vec_flt_result, vec_flt_expected);
-
- vec_flt_expected = (vector float){34.0, 97.0, 214.0, -5.5};
- vec_flt_result = vec_float2 (vec_dble0, vec_dble1);
- test_result_sp(ALL, vec_flt_result, vec_flt_expected);
-
/* conversion of even words in double precision vector to single precision vector */
vec_flt_expected = (vector float){-12.00, 00.00, -12345678901234.00, 0.00};
vec_flt_result = vec_floate (vec_ll_int0);
vec_ll_int_result = vec_signed (vec_dble0);
test_ll_int_result (vec_ll_int_result, vec_ll_int_expected);
- /* Convert two double precision vector float to vector int */
- vec_dble0 = (vector double){-124.930, 81234.49};
- vec_dble1 = (vector double){-24.370, 8354.99};
- vec_int_expected = (vector signed int){-124, 81234, -24, 8354};
- vec_int_result = vec_signed2 (vec_dble0, vec_dble1);
- test_int_result (ALL, vec_int_result, vec_int_expected);
-
/* Convert double precision vector float to vector int, even words */
vec_dble0 = (vector double){-124.930, 81234.49};
vec_int_expected = (vector signed int){-124, 0, 81234, 0};
test_ll_unsigned_int_result (vec_ll_uns_int_result,
vec_ll_uns_int_expected);
- /* Convert two double precision vector float to vector unsigned int */
- vec_dble0 = (vector double){124.930, 8134.49};
- vec_dble1 = (vector double){24.370, 834.99};
- vec_uns_int_expected = (vector unsigned int){124, 8134, 24, 834};
- vec_uns_int_result = vec_unsigned2 (vec_dble0, vec_dble1);
- test_unsigned_int_result (ALL, vec_uns_int_result,
- vec_uns_int_expected);
-
/* Convert double precision vector float to vector unsigned int,
even words */
vec_dble0 = (vector double){3124.930, 8234.49};
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