clk: exynos4: enable clk_set_parent() propagation for sclk_hdmi and sclk_mixer clocks

This patch enables clk_set_parent() propagation for clocks used
by s5p-tv and exynos-drm drivers.

Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com>
Change-Id: I8f91dcd73a43291297def7f69eb35950afd45c55

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 1a3fd05..17979d1 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -608,7 +608,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
         * the device name and clock alias names specified below for some
         * of the clocks can be removed.
         */
-       GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
+       GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0,
+                       CLK_SET_PARENT_PARENT, 0),
        GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0),
        GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
        GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
@@ -818,7 +819,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
                        E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
        GATE(sclk_sata, "sclk_sata", "div_sata",
                        SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
-       GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
+       GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4,
+                       CLK_SET_PARENT_PARENT, 0),
        GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
        GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
        GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"),