--- /dev/null
+/*
+ * Copyright © 2010-2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Zhao Yakui <yakui.zhao@intel.com>
+ * Xiang Haihao <haihao.xiang@intel.com>
+ *
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+
+#include "assert.h"
+#include "intel_batchbuffer.h"
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_encoder.h"
+
+static void
+gen75_mfc_pipe_mode_select(VADriverContextP ctx,
+ int standard_select,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+
+ assert(standard_select == MFX_FORMAT_MPEG2 ||
+ standard_select == MFX_FORMAT_AVC);
+
+ BEGIN_BCS_BATCH(batch, 5);
+ OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
+ OUT_BCS_BATCH(batch,
+ (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
+ (MFD_MODE_VLD << 15) | /* VLD mode */
+ (0 << 10) | /* disable Stream-Out */
+ (1 << 9) | /* Post Deblocking Output */
+ (0 << 8) | /* Pre Deblocking Output */
+ (0 << 5) | /* not in stitch mode */
+ (1 << 4) | /* encoding mode */
+ (standard_select << 0)); /* standard select: avc or mpeg2 */
+ OUT_BCS_BATCH(batch,
+ (0 << 7) | /* expand NOA bus flag */
+ (0 << 6) | /* disable slice-level clock gating */
+ (0 << 5) | /* disable clock gating for NOA */
+ (0 << 4) | /* terminate if AVC motion and POC table error occurs */
+ (0 << 3) | /* terminate if AVC mbdata error occurs */
+ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
+ (0 << 1) |
+ (0 << 0));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen75_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+
+ BEGIN_BCS_BATCH(batch, 6);
+
+ OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch,
+ ((mfc_context->surface_state.height - 1) << 18) |
+ ((mfc_context->surface_state.width - 1) << 4));
+ OUT_BCS_BATCH(batch,
+ (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
+ (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
+ (0 << 22) | /* surface object control state, FIXME??? */
+ ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
+ (0 << 2) | /* must be 0 for interleave U/V */
+ (1 << 1) | /* must be tiled */
+ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
+ OUT_BCS_BATCH(batch,
+ (0 << 16) | /* must be 0 for interleave U/V */
+ (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
+ OUT_BCS_BATCH(batch, 0);
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen75_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ int i;
+
+ BEGIN_BCS_BATCH(batch, 24);
+
+ OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
+
+ OUT_BCS_BATCH(batch, 0); /* pre output addr */
+
+ OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ 0); /* post output addr */
+
+ OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ 0); /* uncompressed data */
+
+ OUT_BCS_BATCH(batch, 0); /* StreamOut data*/
+ OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ 0);
+ OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ 0);
+ /* 7..22 Reference pictures*/
+ for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
+ if ( mfc_context->reference_surfaces[i].bo != NULL) {
+ OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ 0);
+ } else {
+ OUT_BCS_BATCH(batch, 0);
+ }
+ }
+ OUT_BCS_BATCH(batch, 0); /* no block status */
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen75_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+
+ BEGIN_BCS_BATCH(batch, 11);
+
+ OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ /* MFX Indirect MV Object Base Address */
+ OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen75_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+
+ BEGIN_BCS_BATCH(batch, 4);
+
+ OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
+ OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen75_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+
+ int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
+ int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
+
+ BEGIN_BCS_BATCH(batch, 16);
+ OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
+ OUT_BCS_BATCH(batch,
+ ((width_in_mbs * height_in_mbs) & 0xFFFF));
+ OUT_BCS_BATCH(batch,
+ ((height_in_mbs - 1) << 16) |
+ ((width_in_mbs - 1) << 0));
+ OUT_BCS_BATCH(batch,
+ (0 << 24) | /* Second Chroma QP Offset */
+ (0 << 16) | /* Chroma QP Offset */
+ (0 << 14) | /* Max-bit conformance Intra flag */
+ (0 << 13) | /* Max Macroblock size conformance Inter flag */
+ (0 << 12) | /* FIXME: Weighted_Pred_Flag */
+ (0 << 10) | /* FIXME: Weighted_BiPred_Idc */
+ (0 << 8) | /* FIXME: Image Structure */
+ (0 << 0) ); /* Current Decoed Image Frame Store ID, reserved in Encode mode */
+ OUT_BCS_BATCH(batch,
+ (0 << 16) | /* Mininum Frame size */
+ (0 << 15) | /* Disable reading of Macroblock Status Buffer */
+ (0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */
+ (0 << 13) | /* CABAC 0 word insertion test enable */
+ (1 << 12) | /* MVUnpackedEnable,compliant to DXVA */
+ (1 << 10) | /* Chroma Format IDC, 4:2:0 */
+ (0 << 9) | /* FIXME: MbMvFormatFlag */
+ (1 << 7) | /* 0:CAVLC encoding mode,1:CABAC */
+ (0 << 6) | /* Only valid for VLD decoding mode */
+ (0 << 5) | /* Constrained Intra Predition Flag, from PPS */
+ (0 << 4) | /* Direct 8x8 inference flag */
+ (0 << 3) | /* Only 8x8 IDCT Transform Mode Flag */
+ (1 << 2) | /* Frame MB only flag */
+ (0 << 1) | /* MBAFF mode is in active */
+ (0 << 0)); /* Field picture flag */
+ OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */
+ OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */
+ (0xBB8 << 16) | /* InterMbMaxSz */
+ (0xEE8) ); /* IntraMbMaxSz */
+ OUT_BCS_BATCH(batch, 0); /* Reserved */
+ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
+ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
+ OUT_BCS_BATCH(batch, 0x8C000000);
+ OUT_BCS_BATCH(batch, 0x00010000);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void gen75_mfc_avc_directmode_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ int i;
+
+ BEGIN_BCS_BATCH(batch, 69);
+
+ OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
+ //TODO: reference DMV
+ for(i = 0; i < 16; i++){
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ }
+
+ //TODO: current DMV just for test
+#if 0
+ OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[0].bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ 0);
+#else
+ //drm_intel_bo_pin(mfc_context->direct_mv_buffers[0].bo, 0x1000);
+ //OUT_BCS_BATCH(batch, mfc_context->direct_mv_buffers[0].bo->offset);
+ OUT_BCS_BATCH(batch, 0);
+#endif
+
+
+ OUT_BCS_BATCH(batch, 0);
+
+ //TODO: POL list
+ for(i = 0; i < 34; i++) {
+ OUT_BCS_BATCH(batch, 0);
+ }
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void gen75_mfc_avc_slice_state(VADriverContextP ctx,
+ int intra_slice,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+
+ BEGIN_BCS_BATCH(batch, 11);;
+
+ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
+
+ if ( intra_slice )
+ OUT_BCS_BATCH(batch, 2); /*Slice Type: I Slice*/
+ else
+ OUT_BCS_BATCH(batch, 0); /*Slice Type: P Slice*/
+
+ if ( intra_slice )
+ OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/
+ else
+ OUT_BCS_BATCH(batch, 0x00010000); /*1 reference frame*/
+
+ OUT_BCS_BATCH(batch, (0<<24) | /*Enable deblocking operation*/
+ (26<<16) | /*Slice Quantization Parameter*/
+ 0x0202 );
+ OUT_BCS_BATCH(batch, 0); /*First MB X&Y , the postion of current slice*/
+ OUT_BCS_BATCH(batch, ( ((mfc_context->surface_state.height+15)/16) << 16) );
+
+ OUT_BCS_BATCH(batch,
+ (0<<31) | /*RateControlCounterEnable = disable*/
+ (1<<30) | /*ResetRateControlCounter*/
+ (2<<28) | /*RC Triggle Mode = Loose Rate Control*/
+ (1<<19) | /*IsLastSlice*/
+ (0<<18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
+ (0<<17) | /*HeaderPresentFlag*/
+ (1<<16) | /*SliceData PresentFlag*/
+ (0<<15) | /*TailPresentFlag*/
+ (1<<13) | /*RBSP NAL TYPE*/
+ (0<<12) ); /*CabacZeroWordInsertionEnable*/
+
+ OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ mfc_context->mfc_indirect_pak_bse_object.offset);
+
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen75_mfc_qm_state(VADriverContextP ctx,
+ int qm_type,
+ unsigned int *qm,
+ int qm_length,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ unsigned int qm_buffer[16];
+
+ assert(qm_length <= 16);
+ assert(sizeof(*qm) == 4);
+ memcpy(qm_buffer, qm, qm_length * 4);
+
+ BEGIN_BCS_BATCH(batch, 18);
+ OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
+ OUT_BCS_BATCH(batch, qm_type << 0);
+ intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void gen75_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ unsigned int qm[16] = {
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010
+ };
+
+ gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context);
+ gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context);
+ gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context);
+ gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context);
+}
+
+static void
+gen75_mfc_fqm_state(VADriverContextP ctx,
+ int fqm_type,
+ unsigned int *fqm,
+ int fqm_length,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ unsigned int fqm_buffer[32];
+
+ assert(fqm_length <= 32);
+ assert(sizeof(*fqm) == 4);
+ memcpy(fqm_buffer, fqm, fqm_length * 4);
+
+ BEGIN_BCS_BATCH(batch, 34);
+ OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
+ OUT_BCS_BATCH(batch, fqm_type << 0);
+ intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void gen75_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ unsigned int qm[32] = {
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000
+ };
+
+ gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context);
+ gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context);
+ gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context);
+ gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context);
+}
+
+static void gen75_mfc_avc_ref_idx_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ int i;
+
+ BEGIN_BCS_BATCH(batch, 10);
+
+ OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
+ OUT_BCS_BATCH(batch, 0); //Select L0
+
+ OUT_BCS_BATCH(batch, 0x80808000); //Only 1 reference
+ for(i = 0; i < 7; i++) {
+ OUT_BCS_BATCH(batch, 0x80808080);
+ }
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen75_mfc_avc_insert_object(VADriverContextP ctx, int flush_data, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 4);
+
+ OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (4 -2 ) );
+ OUT_BCS_BATCH(batch, (32<<8) |
+ (1 << 3) |
+ (1 << 2) |
+ (flush_data << 1) |
+ (1<<0) );
+ OUT_BCS_BATCH(batch, 0x00000003);
+ OUT_BCS_BATCH(batch, 0xABCD1234);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static int
+gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ int len_in_dwords = 11;
+
+ BEGIN_BCS_BATCH(batch, len_in_dwords);
+
+ OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch,
+ (0 << 24) | /* PackedMvNum, Debug*/
+ (0 << 20) | /* No motion vector */
+ (1 << 19) | /* CbpDcY */
+ (1 << 18) | /* CbpDcU */
+ (1 << 17) | /* CbpDcV */
+ (msg[0] & 0xFFFF) );
+
+ OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
+ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
+ OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
+
+ /*Stuff for Intra MB*/
+ OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
+ OUT_BCS_BATCH(batch, msg[2]);
+ OUT_BCS_BATCH(batch, msg[3]&0xFC);
+
+ OUT_BCS_BATCH(batch, 0x8040000); /*MaxSizeInWord and TargetSzieInWord*/
+
+ ADVANCE_BCS_BATCH(batch);
+
+ return len_in_dwords;
+}
+
+static int gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ int len_in_dwords = 11;
+
+ BEGIN_BCS_BATCH(batch, len_in_dwords);
+
+ OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
+
+ OUT_BCS_BATCH(batch, 32); /* 32 MV*/
+ OUT_BCS_BATCH(batch, offset);
+
+ OUT_BCS_BATCH(batch,
+ (1 << 24) | /* PackedMvNum, Debug*/
+ (4 << 20) | /* 8 MV, SNB don't use it*/
+ (1 << 19) | /* CbpDcY */
+ (1 << 18) | /* CbpDcU */
+ (1 << 17) | /* CbpDcV */
+ (0 << 15) | /* Transform8x8Flag = 0*/
+ (0 << 14) | /* Frame based*/
+ (0 << 13) | /* Inter MB */
+ (1 << 8) | /* MbType = P_L0_16x16 */
+ (0 << 7) | /* MBZ for frame */
+ (0 << 6) | /* MBZ */
+ (2 << 4) | /* MBZ for inter*/
+ (0 << 3) | /* MBZ */
+ (0 << 2) | /* SkipMbFlag */
+ (0 << 0)); /* InterMbMode */
+
+ OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
+ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
+ OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
+
+ /*Stuff for Inter MB*/
+ OUT_BCS_BATCH(batch, 0x0);
+ OUT_BCS_BATCH(batch, 0x0);
+ OUT_BCS_BATCH(batch, 0x0);
+
+ OUT_BCS_BATCH(batch, 0xF0020000); /*MaxSizeInWord and TargetSzieInWord*/
+
+ ADVANCE_BCS_BATCH(batch);
+
+ return len_in_dwords;
+}
+
+static void gen75_mfc_init(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ dri_bo *bo;
+ int i;
+
+ /*Encode common setup for MFC*/
+ dri_bo_unreference(mfc_context->post_deblocking_output.bo);
+ mfc_context->post_deblocking_output.bo = NULL;
+
+ dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
+ mfc_context->pre_deblocking_output.bo = NULL;
+
+ dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
+ mfc_context->uncompressed_picture_source.bo = NULL;
+
+ dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
+ mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
+
+ for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
+ dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
+ mfc_context->direct_mv_buffers[i].bo = NULL;
+ }
+
+ for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
+ if (mfc_context->reference_surfaces[i].bo != NULL)
+ dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
+ mfc_context->reference_surfaces[i].bo = NULL;
+ }
+
+ dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
+ bo = dri_bo_alloc(i965->intel.bufmgr,
+ "Buffer",
+ 128 * 64,
+ 64);
+ assert(bo);
+ mfc_context->intra_row_store_scratch_buffer.bo = bo;
+
+ dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
+ bo = dri_bo_alloc(i965->intel.bufmgr,
+ "Buffer",
+ 49152, /* 6 * 128 * 64 */
+ 64);
+ assert(bo);
+ mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
+
+ dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
+ bo = dri_bo_alloc(i965->intel.bufmgr,
+ "Buffer",
+ 12288, /* 1.5 * 128 * 64 */
+ 0x1000);
+ assert(bo);
+ mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
+}
+
+static void gen75_mfc_avc_pipeline_programing(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
+ VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer; /* FIXME: multi slices */
+ unsigned int *msg = NULL, offset = 0;
+ int emit_new_state = 1, object_len_in_bytes;
+ int is_intra = pSliceParameter->slice_flags.bits.is_intra;
+ int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
+ int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
+ int x,y;
+
+ intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
+
+ if (is_intra) {
+ dri_bo_map(vme_context->vme_output.bo , 1);
+ msg = (unsigned int *)vme_context->vme_output.bo->virtual;
+ }
+
+ for (y = 0; y < height_in_mbs; y++) {
+ for (x = 0; x < width_in_mbs; x++) {
+ int last_mb = (y == (height_in_mbs-1)) && ( x == (width_in_mbs-1) );
+ int qp = pSequenceParameter->initial_qp;
+
+ if (emit_new_state) {
+ intel_batchbuffer_emit_mi_flush(batch);
+
+ gen75_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context);
+ gen75_mfc_surface_state(ctx, gen6_encoder_context);
+ gen75_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
+
+ gen75_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context);
+ gen75_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context);
+
+ gen75_mfc_avc_img_state(ctx, gen6_encoder_context);
+ gen75_mfc_avc_qm_state(ctx, gen6_encoder_context);
+ gen75_mfc_avc_fqm_state(ctx, gen6_encoder_context);
+
+ gen75_mfc_avc_ref_idx_state(ctx, gen6_encoder_context);
+ gen75_mfc_avc_slice_state(ctx, is_intra, gen6_encoder_context);
+ emit_new_state = 0;
+ }
+
+ if (is_intra) {
+ assert(msg);
+ object_len_in_bytes = gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context);
+ msg += 4;
+ } else {
+ object_len_in_bytes = gen75_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, gen6_encoder_context);
+ offset += 64;
+ }
+
+ if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
+ intel_batchbuffer_end_atomic(batch);
+ intel_batchbuffer_flush(batch);
+ emit_new_state = 1;
+ intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
+ }
+ }
+ }
+
+ if (is_intra)
+ dri_bo_unmap(vme_context->vme_output.bo);
+
+ intel_batchbuffer_end_atomic(batch);
+}
+
+static VAStatus gen75_mfc_avc_prepare(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ struct object_surface *obj_surface;
+ struct object_buffer *obj_buffer;
+ dri_bo *bo;
+ VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
+ VAStatus vaStatus = VA_STATUS_SUCCESS;
+
+ /*Setup all the input&output object*/
+ obj_surface = SURFACE(pPicParameter->reconstructed_picture);
+ assert(obj_surface);
+ i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
+ mfc_context->post_deblocking_output.bo = obj_surface->bo;
+ dri_bo_reference(mfc_context->post_deblocking_output.bo);
+
+ mfc_context->surface_state.width = obj_surface->orig_width;
+ mfc_context->surface_state.height = obj_surface->orig_height;
+ mfc_context->surface_state.w_pitch = obj_surface->width;
+ mfc_context->surface_state.h_pitch = obj_surface->height;
+
+ obj_surface = SURFACE(pPicParameter->reference_picture);
+ assert(obj_surface);
+ if (obj_surface->bo != NULL) {
+ mfc_context->reference_surfaces[0].bo = obj_surface->bo;
+ dri_bo_reference(obj_surface->bo);
+ }
+
+ obj_surface = SURFACE(encode_state->current_render_target);
+ assert(obj_surface && obj_surface->bo);
+ mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
+ dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
+
+ obj_buffer = BUFFER (pPicParameter->coded_buf); /* FIXME: fix this later */
+ bo = obj_buffer->buffer_store->bo;
+ assert(bo);
+ mfc_context->mfc_indirect_pak_bse_object.bo = bo;
+ mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64);
+ dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
+
+ /*Programing bcs pipeline*/
+ gen75_mfc_avc_pipeline_programing(ctx, encode_state, gen6_encoder_context); //filling the pipeline
+
+ return vaStatus;
+}
+
+static VAStatus gen75_mfc_run(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+
+ intel_batchbuffer_flush(batch); //run the pipeline
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus gen75_mfc_stop(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+#if 0
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+
+ VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
+
+ struct object_surface *obj_surface = SURFACE(pPicParameter->reconstructed_picture);
+ //struct object_surface *obj_surface = SURFACE(pPicParameter->reference_picture[0]);
+ //struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
+ my_debug(obj_surface);
+
+#endif
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus
+gen75_mfc_avc_encode_picture(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ gen75_mfc_init(ctx, gen6_encoder_context);
+ gen75_mfc_avc_prepare(ctx, encode_state, gen6_encoder_context);
+ gen75_mfc_run(ctx, encode_state, gen6_encoder_context);
+ gen75_mfc_stop(ctx, encode_state, gen6_encoder_context);
+
+ return VA_STATUS_SUCCESS;
+}
+
+VAStatus
+gen75_mfc_pipeline(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ VAStatus vaStatus;
+
+ switch (profile) {
+ case VAProfileH264Baseline:
+ vaStatus = gen75_mfc_avc_encode_picture(ctx, encode_state, gen6_encoder_context);
+ break;
+
+ /* FIXME: add for other profile */
+ default:
+ vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
+ break;
+ }
+
+ return vaStatus;
+}
+
+Bool gen75_mfc_context_init(VADriverContextP ctx, struct gen6_mfc_context *mfc_context)
+{
+ return True;
+}
+
+Bool gen75_mfc_context_destroy(struct gen6_mfc_context *mfc_context)
+{
+ int i;
+
+ dri_bo_unreference(mfc_context->post_deblocking_output.bo);
+ mfc_context->post_deblocking_output.bo = NULL;
+
+ dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
+ mfc_context->pre_deblocking_output.bo = NULL;
+
+ dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
+ mfc_context->uncompressed_picture_source.bo = NULL;
+
+ dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
+ mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
+
+ for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
+ dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
+ mfc_context->direct_mv_buffers[i].bo = NULL;
+ }
+
+ dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
+ mfc_context->intra_row_store_scratch_buffer.bo = NULL;
+
+ dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
+ mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
+
+ dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
+ mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
+
+ return True;
+}
--- /dev/null
+/*
+ * Copyright © 2010-2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Zhao Yakui <yakui.zhao@intel.com>
+ * Xiang HaiHao <haihao.xiang@intel.com>
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+
+#include "i965_defines.h"
+#include "i965_drv_video.h"
+#include "gen6_vme.h"
+#include "i965_encoder.h"
+
+#define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
+#define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32)
+#define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
+
+#define SURFACE_STATE_PADDED_SIZE_0_GEN6 ALIGN(sizeof(struct i965_surface_state), 32)
+#define SURFACE_STATE_PADDED_SIZE_1_GEN6 ALIGN(sizeof(struct i965_surface_state2), 32)
+#define SURFACE_STATE_PADDED_SIZE_GEN6 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN7)
+
+#define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
+#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
+#define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6)
+
+#define VME_INTRA_SHADER 0
+#define VME_INTER_SHADER 1
+
+#define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
+#define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
+#define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
+
+static const uint32_t gen75_vme_intra_frame[][4] = {
+#include "shaders/vme/intra_frame.g7b"
+};
+
+static const uint32_t gen75_vme_inter_frame[][4] = {
+#include "shaders/vme/inter_frame.g7b"
+};
+
+static struct i965_kernel gen75_vme_kernels[] = {
+ {
+ "VME Intra Frame",
+ VME_INTRA_SHADER, /*index*/
+ gen75_vme_intra_frame,
+ sizeof(gen75_vme_intra_frame),
+ NULL
+ },
+ {
+ "VME inter Frame",
+ VME_INTER_SHADER,
+ gen75_vme_inter_frame,
+ sizeof(gen75_vme_inter_frame),
+ NULL
+ }
+};
+
+/*
+ * Surface state for IvyBridge
+ */
+static
+void gen75_vme_set_common_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
+{
+ switch (tiling) {
+ case I915_TILING_NONE:
+ ss->ss0.tiled_surface = 0;
+ ss->ss0.tile_walk = 0;
+ break;
+ case I915_TILING_X:
+ ss->ss0.tiled_surface = 1;
+ ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
+ break;
+ case I915_TILING_Y:
+ ss->ss0.tiled_surface = 1;
+ ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
+ break;
+ }
+}
+
+static void
+gen75_vme_set_source_surface_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
+{
+ switch (tiling) {
+ case I915_TILING_NONE:
+ ss->ss2.tiled_surface = 0;
+ ss->ss2.tile_walk = 0;
+ break;
+ case I915_TILING_X:
+ ss->ss2.tiled_surface = 1;
+ ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
+ break;
+ case I915_TILING_Y:
+ ss->ss2.tiled_surface = 1;
+ ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
+ break;
+ }
+}
+
+
+/* only used for VME source surface state */
+static void gen75_vme_source_surface_state(VADriverContextP ctx,
+ int index,
+ struct object_surface *obj_surface,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ struct gen7_surface_state2 *ss;
+ dri_bo *bo;
+ int w, h, w_pitch, h_pitch;
+ unsigned int tiling, swizzle;
+
+ assert(obj_surface->bo);
+
+ w = obj_surface->orig_width;
+ h = obj_surface->orig_height;
+ w_pitch = obj_surface->width;
+ h_pitch = obj_surface->height;
+
+ bo = vme_context->surface_state_binding_table.bo;
+ dri_bo_map(bo, 1);
+ assert(bo->virtual);
+
+ ss = (struct gen7_surface_state2 *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
+ memset(ss, 0, sizeof(*ss));
+
+ ss->ss0.surface_base_address = obj_surface->bo->offset;
+
+ ss->ss1.cbcr_pixel_offset_v_direction = 2;
+ ss->ss1.width = w - 1;
+ ss->ss1.height = h - 1;
+
+ ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8;
+ ss->ss2.interleave_chroma = 1;
+ ss->ss2.pitch = w_pitch - 1;
+ ss->ss2.half_pitch_for_chroma = 0;
+
+ dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
+ gen75_vme_set_source_surface_tiling(ss, tiling);
+
+ /* UV offset for interleave mode */
+ ss->ss3.x_offset_for_cb = 0;
+ ss->ss3.y_offset_for_cb = h_pitch;
+
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_RENDER, 0,
+ 0,
+ SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
+ obj_surface->bo);
+
+ ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
+ dri_bo_unmap(bo);
+}
+
+static void
+gen75_vme_media_source_surface_state(VADriverContextP ctx,
+ int index,
+ struct object_surface *obj_surface,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ struct gen7_surface_state *ss;
+ dri_bo *bo;
+ int w, h, w_pitch;
+ unsigned int tiling, swizzle;
+
+ /* Y plane */
+ w = obj_surface->orig_width;
+ h = obj_surface->orig_height;
+ w_pitch = obj_surface->width;
+
+ bo = vme_context->surface_state_binding_table.bo;
+ dri_bo_map(bo, True);
+ assert(bo->virtual);
+
+ ss = (struct gen7_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
+ memset(ss, 0, sizeof(*ss));
+
+ ss->ss0.surface_type = I965_SURFACE_2D;
+ ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
+
+ ss->ss1.base_addr = obj_surface->bo->offset;
+
+ ss->ss2.width = w / 4 - 1;
+ ss->ss2.height = h - 1;
+
+ ss->ss3.pitch = w_pitch - 1;
+
+ dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
+ gen75_vme_set_common_surface_tiling(ss, tiling);
+
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_RENDER, 0,
+ 0,
+ SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
+ obj_surface->bo);
+
+ ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
+ dri_bo_unmap(bo);
+}
+
+static VAStatus
+gen75_vme_output_buffer_setup(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ int index,
+ struct gen6_encoder_context *gen6_encoder_context)
+
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ struct gen7_surface_state *ss;
+ dri_bo *bo;
+ VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
+ VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer;
+ int is_intra = pSliceParameter->slice_flags.bits.is_intra;
+ int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
+ int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
+ int num_entries;
+
+ if ( is_intra ) {
+ vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
+ } else {
+ vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs * 4;
+ }
+ vme_context->vme_output.size_block = 16; /* an OWORD */
+ vme_context->vme_output.pitch = ALIGN(vme_context->vme_output.size_block, 16);
+ bo = dri_bo_alloc(i965->intel.bufmgr,
+ "VME output buffer",
+ vme_context->vme_output.num_blocks * vme_context->vme_output.pitch,
+ 0x1000);
+ assert(bo);
+ vme_context->vme_output.bo = bo;
+
+ bo = vme_context->surface_state_binding_table.bo;
+ dri_bo_map(bo, 1);
+ assert(bo->virtual);
+
+ ss = (struct gen7_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
+ ss = bo->virtual;
+ memset(ss, 0, sizeof(*ss));
+
+ /* always use 16 bytes as pitch on Sandy Bridge */
+ num_entries = vme_context->vme_output.num_blocks * vme_context->vme_output.pitch / 16;
+
+ ss->ss0.surface_type = I965_SURFACE_BUFFER;
+
+ ss->ss1.base_addr = vme_context->vme_output.bo->offset;
+
+ ss->ss2.width = ((num_entries - 1) & 0x7f);
+ ss->ss2.height = (((num_entries - 1) >> 7) & 0x3fff);
+ ss->ss3.depth = (((num_entries - 1) >> 21) & 0x3f);
+
+ ss->ss3.pitch = vme_context->vme_output.pitch - 1;
+
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ 0,
+ SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
+ vme_context->vme_output.bo);
+
+ ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
+ dri_bo_unmap(bo);
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus gen75_vme_surface_setup(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ int is_intra,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct object_surface *obj_surface;
+ VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
+
+ /*Setup surfaces state*/
+ /* current picture for encoding */
+ obj_surface = SURFACE(encode_state->current_render_target);
+ assert(obj_surface);
+ gen75_vme_source_surface_state(ctx, 1, obj_surface, gen6_encoder_context);
+ gen75_vme_media_source_surface_state(ctx, 4, obj_surface, gen6_encoder_context);
+
+ if ( ! is_intra ) {
+ /* reference 0 */
+ obj_surface = SURFACE(pPicParameter->reference_picture);
+ assert(obj_surface);
+ gen75_vme_source_surface_state(ctx, 2, obj_surface, gen6_encoder_context);
+ /* reference 1, FIXME: */
+ // obj_surface = SURFACE(pPicParameter->reference_picture);
+ // assert(obj_surface);
+ //gen7_vme_source_surface_state(ctx, 3, obj_surface);
+ }
+
+ /* VME output */
+ gen75_vme_output_buffer_setup(ctx, encode_state, 0, gen6_encoder_context);
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus gen75_vme_interface_setup(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ struct gen6_interface_descriptor_data *desc;
+ int i;
+ dri_bo *bo;
+
+ bo = vme_context->idrt.bo;
+ dri_bo_map(bo, 1);
+ assert(bo->virtual);
+ desc = bo->virtual;
+
+ for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
+ struct i965_kernel *kernel;
+ kernel = &vme_context->vme_kernels[i];
+ assert(sizeof(*desc) == 32);
+ /*Setup the descritor table*/
+ memset(desc, 0, sizeof(*desc));
+ desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
+ desc->desc2.sampler_count = 1; /* FIXME: */
+ desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
+ desc->desc3.binding_table_entry_count = 1; /* FIXME: */
+ desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
+ desc->desc4.constant_urb_entry_read_offset = 0;
+ desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
+
+ /*kernel start*/
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0,
+ i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
+ kernel->bo);
+ /*Sampler State(VME state pointer)*/
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ (1 << 2), //
+ i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
+ vme_context->vme_state.bo);
+ desc++;
+ }
+ dri_bo_unmap(bo);
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus gen75_vme_constant_setup(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ unsigned char *constant_buffer;
+
+ dri_bo_map(vme_context->curbe.bo, 1);
+ assert(vme_context->curbe.bo->virtual);
+ constant_buffer = vme_context->curbe.bo->virtual;
+
+ /*TODO copy buffer into CURB*/
+
+ dri_bo_unmap( vme_context->curbe.bo);
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ int is_intra,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ unsigned int *vme_state_message;
+ int i;
+
+ //building VME state message
+ dri_bo_map(vme_context->vme_state.bo, 1);
+ assert(vme_context->vme_state.bo->virtual);
+ vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
+
+ vme_state_message[0] = 0x10010101;
+ vme_state_message[1] = 0x100F0F0F;
+ vme_state_message[2] = 0x10010101;
+ vme_state_message[3] = 0x000F0F0F;
+ for(i = 4; i < 14; i++) {
+ vme_state_message[i] = 0x00000000;
+ }
+
+ for(i = 14; i < 32; i++) {
+ vme_state_message[i] = 0x00000000;
+ }
+
+ //vme_state_message[16] = 0x42424242; //cost function LUT set 0 for Intra
+
+ dri_bo_unmap( vme_context->vme_state.bo);
+ return VA_STATUS_SUCCESS;
+}
+
+static void gen75_vme_pipeline_select(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+
+ BEGIN_BATCH(batch, 1);
+ OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
+ ADVANCE_BATCH(batch);
+}
+
+static void gen75_vme_state_base_address(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+
+ BEGIN_BATCH(batch, 10);
+
+ OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 8);
+
+ OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); //General State Base Address
+ OUT_RELOC(batch, vme_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
+ OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); //Dynamic State Base Address
+ OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); //Indirect Object Base Address
+ OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); //Instruction Base Address
+
+ OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY); //General State Access Upper Bound
+ OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY); //Dynamic State Access Upper Bound
+ OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY); //Indirect Object Access Upper Bound
+ OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY); //Instruction Access Upper Bound
+
+ /*
+ OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); //LLC Coherent Base Address
+ OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY ); //LLC Coherent Upper Bound
+ */
+
+ ADVANCE_BATCH(batch);
+}
+
+static void gen75_vme_vfe_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+
+ BEGIN_BATCH(batch, 8);
+
+ OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | 6); /*Gen6 CMD_MEDIA_STATE_POINTERS = CMD_MEDIA_STATE */
+ OUT_BATCH(batch, 0); /*Scratch Space Base Pointer and Space*/
+ OUT_BATCH(batch, (vme_context->vfe_state.max_num_threads << 16)
+ | (vme_context->vfe_state.num_urb_entries << 8)
+ | (vme_context->vfe_state.gpgpu_mode << 2) ); /*Maximum Number of Threads , Number of URB Entries, MEDIA Mode*/
+ OUT_BATCH(batch, 0); /*Debug: Object ID*/
+ OUT_BATCH(batch, (vme_context->vfe_state.urb_entry_size << 16)
+ | vme_context->vfe_state.curbe_allocation_size); /*URB Entry Allocation Size , CURBE Allocation Size*/
+ OUT_BATCH(batch, 0); /*Disable Scoreboard*/
+ OUT_BATCH(batch, 0); /*Disable Scoreboard*/
+ OUT_BATCH(batch, 0); /*Disable Scoreboard*/
+
+ ADVANCE_BATCH(batch);
+
+}
+
+static void gen75_vme_curbe_load(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+
+ BEGIN_BATCH(batch, 4);
+
+ OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | 2);
+ OUT_BATCH(batch, 0);
+
+ OUT_BATCH(batch, CURBE_TOTAL_DATA_LENGTH);
+ OUT_RELOC(batch, vme_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+
+ ADVANCE_BATCH(batch);
+}
+
+static void gen75_vme_idrt(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+
+ BEGIN_BATCH(batch, 4);
+
+ OUT_BATCH(batch, CMD_MEDIA_INTERFACE_LOAD | 2);
+ OUT_BATCH(batch, 0);
+ OUT_BATCH(batch, GEN6_VME_KERNEL_NUMBER * sizeof(struct gen6_interface_descriptor_data));
+ OUT_RELOC(batch, vme_context->idrt.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+
+ ADVANCE_BATCH(batch);
+}
+
+static int gen75_vme_media_object(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ int mb_x, int mb_y,
+ int kernel,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
+ int mb_width = ALIGN(obj_surface->orig_width, 16) / 16;
+ int len_in_dowrds = 6 + 1;
+
+ BEGIN_BATCH(batch, len_in_dowrds);
+
+ OUT_BATCH(batch, CMD_MEDIA_OBJECT | (len_in_dowrds - 2));
+ OUT_BATCH(batch, kernel); /*Interface Descriptor Offset*/
+ OUT_BATCH(batch, 0);
+ OUT_BATCH(batch, 0);
+ OUT_BATCH(batch, 0);
+ OUT_BATCH(batch, 0);
+
+ /*inline data */
+ OUT_BATCH(batch, mb_width << 16 | mb_y << 8 | mb_x); /*M0.0 Refrence0 X,Y, not used in Intra*/
+ ADVANCE_BATCH(batch);
+
+ return len_in_dowrds * 4;
+}
+
+static void gen75_vme_media_init(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ dri_bo *bo;
+
+ /* constant buffer */
+ dri_bo_unreference(vme_context->curbe.bo);
+ bo = dri_bo_alloc(i965->intel.bufmgr,
+ "Buffer",
+ CURBE_TOTAL_DATA_LENGTH, 64);
+ assert(bo);
+ vme_context->curbe.bo = bo;
+
+ dri_bo_unreference(vme_context->surface_state_binding_table.bo);
+ bo = dri_bo_alloc(i965->intel.bufmgr,
+ "surface state & binding table",
+ (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6,
+ 4096);
+ assert(bo);
+ vme_context->surface_state_binding_table.bo = bo;
+
+ /* interface descriptor remapping table */
+ dri_bo_unreference(vme_context->idrt.bo);
+ bo = dri_bo_alloc(i965->intel.bufmgr,
+ "Buffer",
+ MAX_INTERFACE_DESC_GEN6 * sizeof(struct gen6_interface_descriptor_data), 16);
+ assert(bo);
+ vme_context->idrt.bo = bo;
+
+ /* VME output buffer */
+ dri_bo_unreference(vme_context->vme_output.bo);
+ vme_context->vme_output.bo = NULL;
+
+ /* VME state */
+ dri_bo_unreference(vme_context->vme_state.bo);
+ bo = dri_bo_alloc(i965->intel.bufmgr,
+ "Buffer",
+ 1024*16, 64);
+ assert(bo);
+ vme_context->vme_state.bo = bo;
+
+ vme_context->vfe_state.max_num_threads = 60 - 1;
+ vme_context->vfe_state.num_urb_entries = 16;
+ vme_context->vfe_state.gpgpu_mode = 0;
+ vme_context->vfe_state.urb_entry_size = 59 - 1;
+ vme_context->vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
+}
+
+static void gen75_vme_pipeline_programing(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer;
+ VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
+ int is_intra = pSliceParameter->slice_flags.bits.is_intra;
+ int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
+ int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
+ int emit_new_state = 1, object_len_in_bytes;
+ int x, y;
+
+ intel_batchbuffer_start_atomic(batch, 0x1000);
+
+ for(y = 0; y < height_in_mbs; y++){
+ for(x = 0; x < width_in_mbs; x++){
+
+ if (emit_new_state) {
+ /*Step1: MI_FLUSH/PIPE_CONTROL*/
+ intel_batchbuffer_emit_mi_flush(batch);
+
+ /*Step2: State command PIPELINE_SELECT*/
+ gen75_vme_pipeline_select(ctx, gen6_encoder_context);
+
+ /*Step3: State commands configuring pipeline states*/
+ gen75_vme_state_base_address(ctx, gen6_encoder_context);
+ gen75_vme_vfe_state(ctx, gen6_encoder_context);
+ gen75_vme_curbe_load(ctx, gen6_encoder_context);
+ gen75_vme_idrt(ctx, gen6_encoder_context);
+
+ emit_new_state = 0;
+ }
+
+ /*Step4: Primitive commands*/
+ object_len_in_bytes = gen75_vme_media_object(ctx, encode_state, x, y, is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER, gen6_encoder_context);
+
+ if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
+ assert(0);
+ intel_batchbuffer_end_atomic(batch);
+ intel_batchbuffer_flush(batch);
+ emit_new_state = 1;
+ intel_batchbuffer_start_atomic(batch, 0x1000);
+ }
+ }
+ }
+
+ intel_batchbuffer_end_atomic(batch);
+}
+
+static VAStatus gen75_vme_prepare(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ VAStatus vaStatus = VA_STATUS_SUCCESS;
+ VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer;
+ int is_intra = pSliceParameter->slice_flags.bits.is_intra;
+
+ gen75_vme_surface_setup(ctx, encode_state, is_intra, gen6_encoder_context);
+
+ gen75_vme_interface_setup(ctx, encode_state, gen6_encoder_context);
+ gen75_vme_constant_setup(ctx, encode_state, gen6_encoder_context);
+ gen75_vme_vme_state_setup(ctx, encode_state, is_intra, gen6_encoder_context);
+
+ /*Programing media pipeline*/
+ gen75_vme_pipeline_programing(ctx, encode_state, gen6_encoder_context);
+
+ return vaStatus;
+}
+
+static VAStatus gen75_vme_run(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+
+ intel_batchbuffer_flush(batch);
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus gen75_vme_stop(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ return VA_STATUS_SUCCESS;
+}
+
+VAStatus gen75_vme_pipeline(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct gen6_encoder_context *gen6_encoder_context)
+{
+ gen75_vme_media_init(ctx, gen6_encoder_context);
+ gen75_vme_prepare(ctx, encode_state, gen6_encoder_context);
+ gen75_vme_run(ctx, encode_state, gen6_encoder_context);
+ gen75_vme_stop(ctx, encode_state, gen6_encoder_context);
+
+ return VA_STATUS_SUCCESS;
+}
+
+Bool gen75_vme_context_init(VADriverContextP ctx, struct gen6_vme_context *vme_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ int i;
+
+ memcpy(vme_context->vme_kernels, gen75_vme_kernels, sizeof(vme_context->vme_kernels));
+
+ for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
+ /*Load kernel into GPU memory*/
+ struct i965_kernel *kernel = &vme_context->vme_kernels[i];
+
+ kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
+ kernel->name,
+ kernel->size,
+ 0x1000);
+ assert(kernel->bo);
+ dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
+ }
+
+ return True;
+}
+
+Bool gen75_vme_context_destroy(struct gen6_vme_context *vme_context)
+{
+ int i;
+
+ dri_bo_unreference(vme_context->idrt.bo);
+ vme_context->idrt.bo = NULL;
+
+ dri_bo_unreference(vme_context->surface_state_binding_table.bo);
+ vme_context->surface_state_binding_table.bo = NULL;
+
+ dri_bo_unreference(vme_context->curbe.bo);
+ vme_context->curbe.bo = NULL;
+
+ dri_bo_unreference(vme_context->vme_output.bo);
+ vme_context->vme_output.bo = NULL;
+
+ dri_bo_unreference(vme_context->vme_state.bo);
+ vme_context->vme_state.bo = NULL;
+
+ for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
+ /*Load kernel into GPU memory*/
+ struct i965_kernel *kernel = &vme_context->vme_kernels[i];
+
+ dri_bo_unreference(kernel->bo);
+ kernel->bo = NULL;
+ }
+
+ return True;
+}
projects / platform / upstream / libva-intel-driver.git / commitdiff