class VMVRSched<int n>: Sched <[!cast<SchedReadWrite>("WriteVMov" # n # "V"),
!cast<SchedReadWrite>("ReadVMov" # n # "V")]>;
-class VLESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDE" # n),
- ReadVLDX, ReadVMask]>;
+class VLESched : Sched <[WriteVLDE, ReadVLDX, ReadVMask]>;
-class VSESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVSTE" # n),
- !cast<SchedReadWrite>("ReadVSTE" # n # "V"),
- ReadVSTX, ReadVMask]>;
+class VSESched : Sched <[WriteVSTE, ReadVSTEV, ReadVSTX, ReadVMask]>;
class VLSSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDS" # n),
ReadVLDX, ReadVLDSX, ReadVMask]>;
!cast<SchedReadWrite>("ReadVST" # o # "X" # n),
ReadVSTX, !cast<SchedReadWrite>("ReadVST" # o # "XV"), ReadVMask]>;
-class VLFSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDFF" # n),
- ReadVLDX, ReadVMask]>;
+class VLFSched : Sched <[WriteVLDFF, ReadVLDX, ReadVMask]>;
// Unit-Stride Segment Loads and Stores
class VLSEGSched<int nf, int eew> : Sched<[
!cast<SchedReadWrite>("WriteVLSEG" #nf #"e" #eew), ReadVLDX, ReadVMask]>;
class VSSEGSched<int nf, int eew> : Sched<[
- !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew),
- !cast<SchedReadWrite>("ReadVSTE" #eew #"V"), ReadVSTX, ReadVMask]>;
+ !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew), ReadVSTEV, ReadVSTX,
+ ReadVMask]>;
class VLSEGFFSched<int nf, int eew> : Sched<[
!cast<SchedReadWrite>("WriteVLSEGFF" #nf #"e" #eew), ReadVLDX, ReadVMask]>;
// Strided Segment Loads and Stores
multiclass VWholeLoadN<bits<3> nf, string opcodestr, RegisterClass VRC> {
foreach l = [8, 16, 32] in {
defvar w = !cast<RISCVWidth>("LSWidth" # l);
- defvar s = !cast<SchedWrite>("WriteVLD" # !add(nf, 1) # "R" # l);
+ defvar s = !cast<SchedWrite>("WriteVLD" # !add(nf, 1) # "R");
def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>,
Sched<[s, ReadVLDX]>;
defvar w = !cast<RISCVWidth>("LSWidth" # eew);
// Vector Unit-Stride Instructions
- def VLE#eew#_V : VUnitStrideLoad<w, "vle"#eew#".v">, VLESched<eew>;
- def VSE#eew#_V : VUnitStrideStore<w, "vse"#eew#".v">, VSESched<eew>;
+ def VLE#eew#_V : VUnitStrideLoad<w, "vle"#eew#".v">, VLESched;
+ def VSE#eew#_V : VUnitStrideStore<w, "vse"#eew#".v">, VSESched;
// Vector Unit-Stride Fault-only-First Loads
- def VLE#eew#FF_V : VUnitStrideLoadFF<w, "vle"#eew#"ff.v">, VLFSched<eew>;
+ def VLE#eew#FF_V : VUnitStrideLoadFF<w, "vle"#eew#"ff.v">, VLFSched;
// Vector Strided Instructions
def VLSE#eew#_V : VStridedLoad<w, "vlse"#eew#".v">, VLSSched<eew>;
let Predicates = [HasVInstructionsI64] in {
// Vector Unit-Stride Instructions
def VLE64_V : VUnitStrideLoad<LSWidth64, "vle64.v">,
- VLESched<64>;
+ VLESched;
def VLE64FF_V : VUnitStrideLoadFF<LSWidth64, "vle64ff.v">,
- VLFSched<64>;
+ VLFSched;
def VSE64_V : VUnitStrideStore<LSWidth64, "vse64.v">,
- VSESched<64>;
+ VSESched;
// Vector Strided Instructions
def VLSE64_V : VStridedLoad<LSWidth64, "vlse64.v">,
VLSSched<32>;
def VSSE64_V : VStridedStore<LSWidth64, "vsse64.v">,
VSSSched<64>;
-defm VL1R: VWholeLoadEEW64<0, "vl1r", VR, WriteVLD1R64>;
-defm VL2R: VWholeLoadEEW64<1, "vl2r", VRM2, WriteVLD2R64>;
-defm VL4R: VWholeLoadEEW64<3, "vl4r", VRM4, WriteVLD4R64>;
-defm VL8R: VWholeLoadEEW64<7, "vl8r", VRM8, WriteVLD8R64>;
+defm VL1R: VWholeLoadEEW64<0, "vl1r", VR, WriteVLD1R>;
+defm VL2R: VWholeLoadEEW64<1, "vl2r", VRM2, WriteVLD2R>;
+defm VL4R: VWholeLoadEEW64<3, "vl4r", VRM4, WriteVLD4R>;
+defm VL8R: VWholeLoadEEW64<7, "vl8r", VRM8, WriteVLD8R>;
} // Predicates = [HasVInstructionsI64]
let Predicates = [IsRV64, HasVInstructionsI64] in {
// Vector Indexed Instructions
// 7. Vector Loads and Stores
// 7.4. Vector Unit-Stride Instructions
-def WriteVLDE8 : SchedWrite;
-def WriteVLDE16 : SchedWrite;
-def WriteVLDE32 : SchedWrite;
-def WriteVLDE64 : SchedWrite;
-def WriteVSTE8 : SchedWrite;
-def WriteVSTE16 : SchedWrite;
-def WriteVSTE32 : SchedWrite;
-def WriteVSTE64 : SchedWrite;
+def WriteVLDE : SchedWrite;
+def WriteVSTE : SchedWrite;
// 7.4.1. Vector Unit-Strided Mask
def WriteVLDM : SchedWrite;
def WriteVSTM : SchedWrite;
def WriteVSTOX32 : SchedWrite;
def WriteVSTOX64 : SchedWrite;
// 7.7. Vector Unit-stride Fault-Only-First Loads
-def WriteVLDFF8 : SchedWrite;
-def WriteVLDFF16 : SchedWrite;
-def WriteVLDFF32 : SchedWrite;
-def WriteVLDFF64 : SchedWrite;
+def WriteVLDFF : SchedWrite;
// 7.8. Vector Segment Instructions
foreach nf=2-8 in {
foreach eew = [8, 16, 32, 64] in {
}
}
// 7.9. Vector Whole Register Instructions
-def WriteVLD1R8 : SchedWrite;
-def WriteVLD1R16 : SchedWrite;
-def WriteVLD1R32 : SchedWrite;
-def WriteVLD1R64 : SchedWrite;
-def WriteVLD2R8 : SchedWrite;
-def WriteVLD2R16 : SchedWrite;
-def WriteVLD2R32 : SchedWrite;
-def WriteVLD2R64 : SchedWrite;
-def WriteVLD4R8 : SchedWrite;
-def WriteVLD4R16 : SchedWrite;
-def WriteVLD4R32 : SchedWrite;
-def WriteVLD4R64 : SchedWrite;
-def WriteVLD8R8 : SchedWrite;
-def WriteVLD8R16 : SchedWrite;
-def WriteVLD8R32 : SchedWrite;
-def WriteVLD8R64 : SchedWrite;
+def WriteVLD1R : SchedWrite;
+def WriteVLD2R : SchedWrite;
+def WriteVLD4R : SchedWrite;
+def WriteVLD8R : SchedWrite;
def WriteVST1R : SchedWrite;
def WriteVST2R : SchedWrite;
def WriteVST4R : SchedWrite;
def ReadVLDX : SchedRead;
def ReadVSTX : SchedRead;
// 7.4. Vector Unit-Stride Instructions
-def ReadVSTE8V : SchedRead;
-def ReadVSTE16V : SchedRead;
-def ReadVSTE32V : SchedRead;
-def ReadVSTE64V : SchedRead;
+def ReadVSTEV : SchedRead;
// 7.4.1. Vector Unit-Strided Mask
def ReadVSTM : SchedRead;
// 7.5. Vector Strided Instructions
def : WriteRes<WriteVSETVL, []>;
// 7. Vector Loads and Stores
-def : WriteRes<WriteVLDE8, []>;
-def : WriteRes<WriteVLDE16, []>;
-def : WriteRes<WriteVLDE32, []>;
-def : WriteRes<WriteVLDE64, []>;
-def : WriteRes<WriteVSTE8, []>;
-def : WriteRes<WriteVSTE16, []>;
-def : WriteRes<WriteVSTE32, []>;
-def : WriteRes<WriteVSTE64, []>;
+def : WriteRes<WriteVLDE, []>;
+def : WriteRes<WriteVSTE, []>;
def : WriteRes<WriteVLDM, []>;
def : WriteRes<WriteVSTM, []>;
def : WriteRes<WriteVLDS8, []>;
def : WriteRes<WriteVSTOX16, []>;
def : WriteRes<WriteVSTOX32, []>;
def : WriteRes<WriteVSTOX64, []>;
-def : WriteRes<WriteVLDFF8, []>;
-def : WriteRes<WriteVLDFF16, []>;
-def : WriteRes<WriteVLDFF32, []>;
-def : WriteRes<WriteVLDFF64, []>;
-def : WriteRes<WriteVLD1R8, []>;
-def : WriteRes<WriteVLD1R16, []>;
-def : WriteRes<WriteVLD1R32, []>;
-def : WriteRes<WriteVLD1R64, []>;
-def : WriteRes<WriteVLD2R8, []>;
-def : WriteRes<WriteVLD2R16, []>;
-def : WriteRes<WriteVLD2R32, []>;
-def : WriteRes<WriteVLD2R64, []>;
-def : WriteRes<WriteVLD4R8, []>;
-def : WriteRes<WriteVLD4R16, []>;
-def : WriteRes<WriteVLD4R32, []>;
-def : WriteRes<WriteVLD4R64, []>;
-def : WriteRes<WriteVLD8R8, []>;
-def : WriteRes<WriteVLD8R16, []>;
-def : WriteRes<WriteVLD8R32, []>;
-def : WriteRes<WriteVLD8R64, []>;
+def : WriteRes<WriteVLDFF, []>;
+def : WriteRes<WriteVLD1R, []>;
+def : WriteRes<WriteVLD2R, []>;
+def : WriteRes<WriteVLD4R, []>;
+def : WriteRes<WriteVLD8R, []>;
def : WriteRes<WriteVST1R, []>;
def : WriteRes<WriteVST2R, []>;
def : WriteRes<WriteVST4R, []>;
// 7. Vector Loads and Stores
def : ReadAdvance<ReadVLDX, 0>;
def : ReadAdvance<ReadVSTX, 0>;
-def : ReadAdvance<ReadVSTE8V, 0>;
-def : ReadAdvance<ReadVSTE16V, 0>;
-def : ReadAdvance<ReadVSTE32V, 0>;
-def : ReadAdvance<ReadVSTE64V, 0>;
+def : ReadAdvance<ReadVSTEV, 0>;
def : ReadAdvance<ReadVSTM, 0>;
def : ReadAdvance<ReadVLDSX, 0>;
def : ReadAdvance<ReadVSTSX, 0>;