riscv: dts: thead: Add GPU node and dependent nodes 34/316034/2
authorMichal Wilczynski <m.wilczynski@samsung.com>
Fri, 9 Aug 2024 16:04:27 +0000 (18:04 +0200)
committerMichal Wilczynski <m.wilczynski@samsung.com>
Tue, 13 Aug 2024 08:21:59 +0000 (10:21 +0200)
GPU device tree node is dependent on always-on module working correctly.
Fix aon node by supplying it with correct reserved memory space. Add the
gpu node itself. Add an empty aon node in the beaglev-ahead dts, to
avoid breaking the compilation.

Change-Id: I9eafb0d576b1045089a640419ee7a0400ba90550
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
arch/riscv/boot/dts/thead/th1520.dtsi

index d9b4de9e4757421dfffdf68a6ddfe574a9f28822..0e6f1a0d85735356d81fad8565ea98936e527b3d 100644 (file)
                reg = <0x0  0x00000000  0x1 0x00000000>;
 
        };
+
+       aon: aon {
+               compatible = "thead,light-aon";
+               mbox-names = "aon";
+               mboxes = <&mbox_910t 1 0>;
+               status = "disabled";
+
+               pd: light-aon-pd {
+                       compatible = "thead,light-aon-pd";
+                       #power-domain-cells = <1>;
+               };
+       };
+
 };
 
 &osc {
index 52f3c4c68d5a09e2e77b55407a2f36ea20bf61a7..2efe93fba6b2f1d7737b9b8501d4894610963f2d 100644 (file)
                mboxes = <&mbox_910t 1 0>;
                status = "okay";
 
+               log-memory-region = <&aon_log_mem>;
+
                pd: light-aon-pd {
                        compatible = "thead,light-aon-pd";
                        #power-domain-cells = <1>;
        };
 };
 
+&resmem {
+       #address-cells = <2>;
+       #size-cells = <2>;
+       ranges;
+       aon_log_mem: memory@33600000 {
+               reg = <0x0 0x33600000 0x0 0x200000>;
+       };
+};
+
 &padctrl1_apsys {
        light-evb-padctrl1 {
                /*
        max-frequency = <198000000>;
        status = "okay";
 };
+
+&gpu {
+       status = "okay";
+};
index decf16d3a7c77de83c22dd6040d38895d4805ad6..6a03e059f16968b02bfd27dcdf29e8035d7984a9 100644 (file)
 #include <dt-bindings/clock/light-vosys.h>
 #include <dt-bindings/pinctrl/light-fm-left-pinctrl.h>
 #include <dt-bindings/pinctrl/light-fm-right-pinctrl.h>
+#include <dt-bindings/firmware/thead/rsrc.h>
 
 / {
        compatible = "thead,th1520";
        #address-cells = <2>;
        #size-cells = <2>;
 
+       resmem: reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               /* global autoconfigured region for contiguous allocations */
+               cmamem: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0 0x14000000>; // 320MB by default
+                       alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
+                       linux,cma-default;
+               };
+       };
+
+
        cpus: cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                        status = "disabled";
                };
 
+               gpu: gpu@ffef400000 {
+                       compatible = "img,gpu";
+                       reg = <0xff 0xef400000 0x0 0x100000>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "gpuirq";
+                       vosys-regmap = <&vosys_reg>;
+                       power-domains = <&pd LIGHT_AON_GPU_PD>;
+                       clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>,
+                                <&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>;
+                       clock-names = "cclk", "aclk";
+                       gpu_clk_rate = <18000000>;
+                       dma-mask = <0xf 0xffffffff>;
+                       status = "disabled";
+               };
+
                stmmac_axi_setup: stmmac-axi-config {
                        snps,wr_osr_lmt = <3>;
                        snps,rd_osr_lmt = <3>;