svga: set PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY for VGPU10 device

Instead of forcing vertex buffer stride to be 4 byte aligned only,
DX10 actually allows the stride to be non 4-byte aligned but the
alignment of an element must be the nearest power of 2 greater or equal to the
width of the element's format, or 4, whichever is less.  So the requirement is
better met with PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY which if set to
TRUE, the sum of vertex element offset + vertex buffer offset + vertex buffer
stride must be aligned to the vertex attributes component size.
Note: PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY cannot be set
with other alignment-requiring CAPs, so we have to return 0 for all the
other alignement CAPs.

This avoids some unnecessary software vertex translate fallback.

cc: mesa-stable

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22689>

diff --git a/src/gallium/drivers/svga/svga_cmd_vgpu10.c b/src/gallium/drivers/svga/svga_cmd_vgpu10.c
index d87cf01..3382921 100644 (file)
--- a/src/gallium/drivers/svga/svga_cmd_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_cmd_vgpu10.c
@@ -853,7 +853,6 @@ SVGA3D_vgpu10_DefineElementLayout(struct svga_winsys_context *swc,
                                   const SVGA3dInputElementDesc *elements)
 {
    SVGA3dCmdDXDefineElementLayout *cmd;
-   unsigned i;
 
    cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT,
                             sizeof(SVGA3dCmdDXDefineElementLayout) +
@@ -861,12 +860,6 @@ SVGA3D_vgpu10_DefineElementLayout(struct svga_winsys_context *swc,
    if (!cmd)
       return PIPE_ERROR_OUT_OF_MEMORY;
 
-   /* check that all offsets are multiples of four */
-   for (i = 0; i < count; i++) {
-      assert(elements[i].alignedByteOffset % 4 == 0);
-   }
-   (void) i; /* silence unused var in release build */
-
    cmd->elementLayoutId = elementLayoutId;
    memcpy(cmd + 1, elements, count * sizeof(SVGA3dInputElementDesc));
 
@@ -1194,8 +1187,6 @@ SVGA3D_vgpu10_SetVertexBuffers(struct svga_winsys_context *swc,
    for (i = 0; i < count; i++) {
       bufs[i].stride = bufferInfo[i].stride;
       bufs[i].offset = bufferInfo[i].offset;
-      assert(bufs[i].stride % 4 == 0);
-      assert(bufs[i].offset % 4 == 0);
       swc->surface_relocation(swc, &bufs[i].sid, NULL, surfaces[i],
                               SVGA_RELOC_READ);
    }
@@ -1231,8 +1222,6 @@ SVGA3D_vgpu10_SetVertexBuffersOffsetAndSize(struct svga_winsys_context *swc,
       bufs[i].stride = bufferInfo[i].stride;
       bufs[i].offset = bufferInfo[i].offset;
       bufs[i].sizeInBytes = bufferInfo[i].sizeInBytes;
-      assert(bufs[i].stride % 4 == 0);
-      assert(bufs[i].offset % 4 == 0);
    }
 
    swc->commit(swc);

diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c
index 426c8e4..53a870d 100644 (file)
--- a/src/gallium/drivers/svga/svga_screen.c
+++ b/src/gallium/drivers/svga/svga_screen.c
@@ -406,9 +406,13 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
       return 64;
    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
+      return sws->have_vgpu10 ? 0 : 1;
+   case PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY:
+      /* This CAP cannot be used with any other alignment-requiring CAPs */
+      return sws->have_vgpu10 ? 1 : 0;
    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
-      return 1;  /* need 4-byte alignment for all offsets and strides */
+      return sws->have_vgpu10 ? 0 : 1;
    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
       return 2048;
    case PIPE_CAP_MAX_VIEWPORTS: