+Thu Mar 6 16:51:11 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these
+ as relaxable.
+
+Tue Mar 4 06:10:36 1997 J.T. Conklin <jtc@cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010.
+
Mon Mar 3 07:45:20 1997 J.T. Conklin <jtc@cygnus.com>
* m68k-opc.c (m68k_opcodes): Added entries for the tst insns on
Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com)
* mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative
- branchs relaxable.
+ branches relaxable.
Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com>
/* 16 bit pc-relative immediate which may promote to a 16bit
pc-relative immediate. */
#define IMM16_PCREL (IMM16+1)
- {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},
+ {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
/* 16bit unsigned dispacement in a memory operation which
may promote to a 32bit displacement. */
/* 8 bit pc-relative displacement. */
#define SD8N_PCREL (SD8N+1)
- {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL},
+ {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
/* 8 bit signed displacement shifted left 8 bits in the instruction. */
#define SD8N_SHIFT8 (SD8N_PCREL+1)
/* 16bit pc-relative displacement which may promote to 32bit pc-relative
displacement. */
#define D16_SHIFT (AN01+1)
- {16, 8, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},
+ {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
/* 8 bit immediate found in the extension word. */
#define IMM8E (D16_SHIFT+1)