+2016-02-02 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.c
+ (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define.
+ (aarch64_ira_change_pseudo_allocno_class): New function.
+
2016-02-02 Uros Bizjak <ubizjak@gmail.com>
PR target/67032
error ("%qs feature modifier is incompatible with %s %s", "+nofp", mc, msg);
}
+/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
+ The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
+ the same cost even if ALL_REGS has a much larger cost. This results in bad
+ allocations and spilling. To avoid this we force the class to GENERAL_REGS
+ if the mode is integer. */
+
+static reg_class_t
+aarch64_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class)
+{
+ enum machine_mode mode;
+
+ if (allocno_class != ALL_REGS)
+ return allocno_class;
+
+ mode = PSEUDO_REGNO_MODE (regno);
+ return FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode) ? FP_REGS : GENERAL_REGS;
+}
+
static unsigned int
aarch64_min_divisions_for_recip_mul (enum machine_mode mode)
{
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS aarch64_init_builtins
+#undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
+#define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
+ aarch64_ira_change_pseudo_allocno_class
+
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
+2016-02-02 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * gcc.target/aarch64/scalar_shift_1.c
+ (test_corners_sisd_di): Improve force to SIMD register.
+ (test_corners_sisd_si): Likewise.
+ * gcc.target/aarch64/vect-ld1r-compile-fp.c:
+ Remove scan-assembler check for ldr.
+
2016-02-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/69595