PCI: qcom: Add support for SA8540P
authorJohan Hovold <johan+linaro@kernel.org>
Thu, 14 Jul 2022 07:13:45 +0000 (09:13 +0200)
committerLorenzo Pieralisi <lpieralisi@kernel.org>
Tue, 23 Aug 2022 07:25:11 +0000 (09:25 +0200)
The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane
and one 1-lane.

Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops.

Note that like for SC8280XP, the SA8540P controllers need two or three
interconnect clocks to be enabled.

Link: https://lore.kernel.org/r/20220714071348.6792-6-johan+linaro@kernel.org
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
drivers/pci/controller/dwc/pcie-qcom.c

index 11841f2..260961f 100644 (file)
@@ -1633,6 +1633,11 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
        .ops = &ops_2_4_0,
 };
 
+static const struct qcom_pcie_cfg sa8540p_cfg = {
+       .ops = &ops_1_9_0,
+       .has_ddrss_sf_tbu_clk = true,
+};
+
 static const struct qcom_pcie_cfg sc8280xp_cfg = {
        .ops = &ops_1_9_0,
        .has_ddrss_sf_tbu_clk = true,
@@ -1786,6 +1791,7 @@ static const struct of_device_id qcom_pcie_match[] = {
        { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
        { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
        { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
+       { .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg },
        { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
        { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
        { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },