has_ssse3_(false),
has_sse41_(false),
has_sse42_(false),
+ is_atom_(false),
has_avx_(false),
has_fma3_(false),
has_idiva_(false),
has_sse42_ = (cpu_info[2] & 0x00100000) != 0;
has_avx_ = (cpu_info[2] & 0x10000000) != 0;
if (has_avx_) has_fma3_ = (cpu_info[2] & 0x00001000) != 0;
+
+ if (family_ == 0x6) {
+ switch (model_) {
+ case 0x1c: // SLT
+ case 0x26:
+ case 0x36:
+ case 0x27:
+ case 0x35:
+ case 0x37: // SLM
+ case 0x4a:
+ case 0x4d:
+ is_atom_ = true;
+ }
+ }
}
#if V8_HOST_ARCH_IA32
bool has_sse42() const { return has_sse42_; }
bool has_avx() const { return has_avx_; }
bool has_fma3() const { return has_fma3_; }
+ bool is_atom() const { return is_atom_; }
// arm features
bool has_idiva() const { return has_idiva_; }
bool has_ssse3_;
bool has_sse41_;
bool has_sse42_;
+ bool is_atom_;
bool has_avx_;
bool has_fma3_;
bool has_idiva_;
for (auto i = buffer.pushed_nodes.rbegin(); i != buffer.pushed_nodes.rend();
++i) {
// TODO(titzer): handle pushing double parameters.
- Emit(kIA32Push, nullptr,
- g.CanBeImmediate(*i) ? g.UseImmediate(*i) : g.Use(*i));
+ InstructionOperand* value =
+ g.CanBeImmediate(*i) ? g.UseImmediate(*i) : IsSupported(ATOM)
+ ? g.UseRegister(*i)
+ : g.Use(*i);
+ Emit(kIA32Push, nullptr, value);
}
// Select the appropriate opcode based on the call type.
for (auto i = buffer.pushed_nodes.rbegin(); i != buffer.pushed_nodes.rend();
++i) {
// TODO(titzer): handle pushing double parameters.
- Emit(kX64Push, nullptr,
- g.CanBeImmediate(*i) ? g.UseImmediate(*i) : g.Use(*i));
+ InstructionOperand* value =
+ g.CanBeImmediate(*i) ? g.UseImmediate(*i) : IsSupported(ATOM)
+ ? g.UseRegister(*i)
+ : g.Use(*i);
+ Emit(kX64Push, nullptr, value);
}
// Select the appropriate opcode based on the call type.
"enable use of constant pools for double immediate (ARM only)")
DEFINE_BOOL(force_long_branches, false,
"force all emitted branches to be in long mode (MIPS/PPC only)")
+DEFINE_STRING(mcpu, "auto", "enable optimization for specific cpu")
// bootstrapper.cc
DEFINE_STRING(expose_natives_as, NULL, "expose natives in global object")
SAHF,
AVX,
FMA3,
+ ATOM,
// ARM
VFP3,
ARMv7,
if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
if (cpu.has_avx() && EnableAVX()) supported_ |= 1u << AVX;
if (cpu.has_fma3() && FLAG_enable_fma3) supported_ |= 1u << FMA3;
+ if (strcmp(FLAG_mcpu, "auto") == 0) {
+ if (cpu.is_atom()) supported_ |= 1u << ATOM;
+ } else if (strcmp(FLAG_mcpu, "atom") == 0) {
+ supported_ |= 1u << ATOM;
+ }
}
void CpuFeatures::PrintTarget() { }
void CpuFeatures::PrintFeatures() {
- printf("SSE3=%d SSE4_1=%d AVX=%d FMA3=%d\n", CpuFeatures::IsSupported(SSE3),
- CpuFeatures::IsSupported(SSE4_1), CpuFeatures::IsSupported(AVX),
- CpuFeatures::IsSupported(FMA3));
+ printf("SSE3=%d SSE4_1=%d AVX=%d FMA3=%d ATOM=%d\n",
+ CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSE4_1),
+ CpuFeatures::IsSupported(AVX), CpuFeatures::IsSupported(FMA3),
+ CpuFeatures::IsSupported(ATOM));
}
if (cpu.has_sahf() && FLAG_enable_sahf) supported_ |= 1u << SAHF;
if (cpu.has_avx() && EnableAVX()) supported_ |= 1u << AVX;
if (cpu.has_fma3() && FLAG_enable_fma3) supported_ |= 1u << FMA3;
+ if (strcmp(FLAG_mcpu, "auto") == 0) {
+ if (cpu.is_atom()) supported_ |= 1u << ATOM;
+ } else if (strcmp(FLAG_mcpu, "atom") == 0) {
+ supported_ |= 1u << ATOM;
+ }
}
void CpuFeatures::PrintTarget() { }
void CpuFeatures::PrintFeatures() {
- printf("SSE3=%d SSE4_1=%d SAHF=%d AVX=%d FMA3=%d\n",
+ printf("SSE3=%d SSE4_1=%d SAHF=%d AVX=%d FMA3=%d ATOM=%d\n",
CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSE4_1),
CpuFeatures::IsSupported(SAHF), CpuFeatures::IsSupported(AVX),
- CpuFeatures::IsSupported(FMA3));
+ CpuFeatures::IsSupported(FMA3), CpuFeatures::IsSupported(ATOM));
}
void MacroAssembler::Call(const Operand& op) {
- if (kPointerSize == kInt64Size) {
+ if (kPointerSize == kInt64Size && !CpuFeatures::IsSupported(ATOM)) {
call(op);
} else {
movp(kScratchRegister, op);