winsys/amdgpu: fix (enable) preemption for chained IBs

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19131>

diff --git a/src/amd/registers/pkt3.json b/src/amd/registers/pkt3.json
index e54196e..bdee735 100644 (file)
--- a/src/amd/registers/pkt3.json
+++ b/src/amd/registers/pkt3.json
@@ -496,6 +496,7 @@
    "fields": [
     {"bits": [0, 19], "name": "IB_SIZE"},
     {"bits": [20, 20], "name": "CHAIN"},
+    {"bits": [21, 21], "name": "PRE_ENA"},
     {"bits": [23, 23], "name": "VALID"}
    ]
   },

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a6cb9d8..3b6f3ab 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -824,7 +824,8 @@ static void amdgpu_set_ib_size(struct radeon_cmdbuf *rcs, struct amdgpu_ib *ib)
 {
    if (ib->ptr_ib_size_inside_ib) {
       *ib->ptr_ib_size = rcs->current.cdw |
-                         S_3F2_CHAIN(1) | S_3F2_VALID(1);
+                         S_3F2_CHAIN(1) | S_3F2_VALID(1) |
+                         S_3F2_PRE_ENA(((struct amdgpu_cs*)ib)->preamble_ib_bo != NULL);
    } else {
       *ib->ptr_ib_size = rcs->current.cdw;
    }