arm64: ls1043a: Remove the workaround of erratum A-009929
authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Thu, 25 Jun 2020 14:23:53 +0000 (22:23 +0800)
committerPriyanka Jain <priyanka.jain@nxp.com>
Mon, 27 Jul 2020 08:46:28 +0000 (14:16 +0530)
The workaround has been implemented in PBI phase, so remove
the duplicated implementation from U-Boot.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/soc.c

index bfc8473..be51b7d 100644 (file)
@@ -68,7 +68,6 @@ config ARCH_LS1043A
        select SYS_FSL_ERRATUM_A009660 if !TFABOOT
        select SYS_FSL_ERRATUM_A009663 if !TFABOOT
        select SYS_FSL_ERRATUM_A009798
-       select SYS_FSL_ERRATUM_A009929
        select SYS_FSL_ERRATUM_A009942 if !TFABOOT
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A010539
@@ -592,9 +591,6 @@ config SYS_FSL_ERRATUM_A009635
 config SYS_FSL_ERRATUM_A009660
        bool
 
-config SYS_FSL_ERRATUM_A009929
-       bool
-
 config SYS_FSL_ERRATUM_A050382
        bool
 
index ad7ea05..0cd8e92 100644 (file)
@@ -445,20 +445,6 @@ int get_core_volt_from_fuse(void)
 }
 
 #elif defined(CONFIG_FSL_LSCH2)
-
-static void erratum_a009929(void)
-{
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
-       struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-       u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
-       u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
-
-       rstrqmr1 |= 0x00000400;
-       gur_out32(&gur->rstrqmr1, rstrqmr1);
-       writel(0x01000000, dcsr_cop_ccp);
-#endif
-}
-
 /*
  * This erratum requires setting a value to eddrtqcr1 to optimal
  * the DDR performance. The eddrtqcr1 register is in SCFG space
@@ -724,7 +710,6 @@ void fsl_lsch2_early_init_f(void)
 #endif
        /* Erratum */
        erratum_a008850_early(); /* part 1 of 2 */
-       erratum_a009929();
        erratum_a009660();
        erratum_a010539();
        erratum_a009008();