drm/amdgpu: define the TMZ bit for the PTE

Define the TMZ (encryption) bit in the page table entry (PTE) for
Raven and newer asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index b13c14d6b82030055bb9a1501d3b3ae97380d5e2..fd61466dc226ed39c95b811432c3cb3ba1a6e8b4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -54,6 +54,9 @@ struct amdgpu_bo_list_entry;
 #define AMDGPU_PTE_SYSTEM      (1ULL << 1)
 #define AMDGPU_PTE_SNOOPED     (1ULL << 2)
 
+/* RV+ */
+#define AMDGPU_PTE_TMZ         (1ULL << 3)
+
 /* VI only */
 #define AMDGPU_PTE_EXECUTABLE  (1ULL << 4)