drm/amdgpu: implement PSP cmd GFX_CMD_ID_PROG_REG

Add implementation to program regs by PSP, currently the following
IH registers are supported:
	IH_RB_CNTL
	IH_RB_CNTL_RING1
	IH_RB_CNTL_RING2

Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 05897b0..c567a55 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -289,6 +289,34 @@ static int psp_asd_load(struct psp_context *psp)
        return ret;
 }
 
+static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+               uint32_t id, uint32_t value)
+{
+       cmd->cmd_id = GFX_CMD_ID_PROG_REG;
+       cmd->cmd.cmd_setup_reg_prog.reg_value = value;
+       cmd->cmd.cmd_setup_reg_prog.reg_id = id;
+}
+
+int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
+               uint32_t value)
+{
+       struct psp_gfx_cmd_resp *cmd = NULL;
+       int ret = 0;
+
+       if (reg >= PSP_REG_LAST)
+               return -EINVAL;
+
+       cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+       if (!cmd)
+               return -ENOMEM;
+
+       psp_prep_reg_prog_cmd_buf(cmd, reg, value);
+       ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
+
+       kfree(cmd);
+       return ret;
+}
+
 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
                                          uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
                                          uint32_t xgmi_ta_size, uint32_t shared_size)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index acbc18b..cf49539 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -62,6 +62,14 @@ struct psp_ring
        uint32_t                        ring_size;
 };
 
+/* More registers may will be supported */
+enum psp_reg_prog_id {
+       PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
+       PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
+       PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
+       PSP_REG_LAST
+};
+
 struct psp_funcs
 {
        int (*init_microcode)(struct psp_context *psp);
@@ -252,5 +260,6 @@ int psp_ras_enable_features(struct psp_context *psp,
                union ta_ras_cmd_input *info, bool enable);
 
 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
-
+int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
+               uint32_t value);
 #endif