net/mlx5: Lag, set active ports if support bypass port select flow table

active_port bit mask indicates the current active ports. Set bit indicates
the port is active. Update active ports info to FW to redirect the QP/TIS
from inactive ports to other ports.

Signed-off-by: Liu, Changcheng <jerrliu@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
index 4cc5fc3..90d3054 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
@@ -65,6 +65,21 @@ static int get_port_sel_mode(enum mlx5_lag_mode mode, unsigned long flags)
        return MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY;
 }
 
+static u8 lag_active_port_bits(struct mlx5_lag *ldev)
+{
+       u8 enabled_ports[MLX5_MAX_PORTS] = {};
+       u8 active_port = 0;
+       int num_enabled;
+       int idx;
+
+       mlx5_infer_tx_enabled(&ldev->tracker, ldev->ports, enabled_ports,
+                             &num_enabled);
+       for (idx = 0; idx < num_enabled; idx++)
+               active_port |= BIT_MASK(enabled_ports[idx]);
+
+       return active_port;
+}
+
 static int mlx5_cmd_create_lag(struct mlx5_core_dev *dev, u8 *ports, int mode,
                               unsigned long flags)
 {
@@ -77,9 +92,21 @@ static int mlx5_cmd_create_lag(struct mlx5_core_dev *dev, u8 *ports, int mode,
        lag_ctx = MLX5_ADDR_OF(create_lag_in, in, ctx);
        MLX5_SET(create_lag_in, in, opcode, MLX5_CMD_OP_CREATE_LAG);
        MLX5_SET(lagc, lag_ctx, fdb_selection_mode, fdb_sel_mode);
-       if (port_sel_mode == MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY) {
+
+       switch (port_sel_mode) {
+       case MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY:
                MLX5_SET(lagc, lag_ctx, tx_remap_affinity_1, ports[0]);
                MLX5_SET(lagc, lag_ctx, tx_remap_affinity_2, ports[1]);
+               break;
+       case MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT:
+               if (!MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass))
+                       break;
+
+               MLX5_SET(lagc, lag_ctx, active_port,
+                        lag_active_port_bits(mlx5_lag_dev(dev)));
+               break;
+       default:
+               break;
        }
        MLX5_SET(lagc, lag_ctx, port_select_mode, port_sel_mode);
 
@@ -386,12 +413,37 @@ static void mlx5_lag_drop_rule_setup(struct mlx5_lag *ldev,
        }
 }
 
+static int mlx5_cmd_modify_active_port(struct mlx5_core_dev *dev, u8 ports)
+{
+       u32 in[MLX5_ST_SZ_DW(modify_lag_in)] = {};
+       void *lag_ctx;
+
+       lag_ctx = MLX5_ADDR_OF(modify_lag_in, in, ctx);
+
+       MLX5_SET(modify_lag_in, in, opcode, MLX5_CMD_OP_MODIFY_LAG);
+       MLX5_SET(modify_lag_in, in, field_select, 0x2);
+
+       MLX5_SET(lagc, lag_ctx, active_port, ports);
+
+       return mlx5_cmd_exec_in(dev, modify_lag, in);
+}
+
 static int _mlx5_modify_lag(struct mlx5_lag *ldev, u8 *ports)
 {
        struct mlx5_core_dev *dev0 = ldev->pf[MLX5_LAG_P1].dev;
+       u8 active_ports;
+       int ret;
 
-       if (test_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, &ldev->mode_flags))
-               return mlx5_lag_port_sel_modify(ldev, ports);
+       if (test_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, &ldev->mode_flags)) {
+               ret = mlx5_lag_port_sel_modify(ldev, ports);
+               if (ret ||
+                   !MLX5_CAP_PORT_SELECTION(dev0, port_select_flow_table_bypass))
+                       return ret;
+
+               active_ports = lag_active_port_bits(ldev);
+
+               return mlx5_cmd_modify_active_port(dev0, active_ports);
+       }
        return mlx5_cmd_modify_lag(dev0, ldev->ports, ports);
 }