[AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32

See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41186

llvm-svn: 321367

diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 7ecaf0b..25a4420 100644 (file)
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -3852,7 +3852,9 @@ AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) {
 
     return Ok? MatchOperand_Success : MatchOperand_ParseFail;
   } else {
-    return MatchOperand_NoMatch;
+    // Swizzle "offset" operand is optional.
+    // If it is omitted, try parsing other optional operands.
+    return parseOptionalOperand(Operands);
   }
 }
 

diff --git a/llvm/test/MC/AMDGPU/ds.s b/llvm/test/MC/AMDGPU/ds.s
index ef36a98..b06101a 100644 (file)
--- a/llvm/test/MC/AMDGPU/ds.s
+++ b/llvm/test/MC/AMDGPU/ds.s
@@ -511,6 +511,10 @@ ds_swizzle_b32 v8, v2
 // SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
 // VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
 
+ds_swizzle_b32 v8, v2 gds
+// SICI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0xd6,0xd8,0x02,0x00,0x00,0x08]
+// VI:   ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
+
 ds_swizzle_b32 v8, v2 offset:0xFFFF
 // SICI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x02,0x00,0x00,0x08]
 // VI:   ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x02,0x00,0x00,0x08]

diff --git a/llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt
index 6d910ea..c12e7a1 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt
@@ -171,6 +171,9 @@
 # VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08
 
+# VI:   ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
+0x00 0x00 0x7b 0xd8 0x02 0x00 0x00 0x08
+
 # VI:   ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08