ARM: imx: Add msl code support for imx6qp
authorBai Ping <ping.bai@nxp.com>
Tue, 2 Feb 2016 10:01:38 +0000 (18:01 +0800)
committerShawn Guo <shawnguo@kernel.org>
Sun, 14 Feb 2016 03:07:17 +0000 (11:07 +0800)
The i.MX6QP is a different SOC, but internally we treate it as i.MX6Q
Rev_2.0 to maximum the code reusability. The chip silicon number we
read from the ANADIG_DIGPROG is 0x630100. This patch add code to
identify it as i.MX6QP Rev_1.0 when print out the silicon version.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/mach-imx/anatop.c
arch/arm/mach-imx/mach-imx6q.c

index bd3555e..649a84c 100644 (file)
@@ -129,7 +129,14 @@ void __init imx_init_revision_from_anatop(void)
 
        switch (digprog & 0xff) {
        case 0:
-               revision = IMX_CHIP_REVISION_1_0;
+               /*
+                * For i.MX6QP, most of the code for i.MX6Q can be resued,
+                * so internally, we identify it as i.MX6Q Rev 2.0
+                */
+               if (digprog >> 8 & 0x01)
+                       revision = IMX_CHIP_REVISION_2_0;
+               else
+                       revision = IMX_CHIP_REVISION_1_0;
                break;
        case 1:
                revision = IMX_CHIP_REVISION_1_1;
index 3878494..cb27d56 100644 (file)
@@ -266,8 +266,11 @@ static void __init imx6q_init_machine(void)
 {
        struct device *parent;
 
-       imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
-                             imx_get_soc_revision());
+       if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+               imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
+       else
+               imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
+                               imx_get_soc_revision());
 
        parent = imx_soc_device_init();
        if (parent == NULL)
@@ -399,6 +402,7 @@ static void __init imx6q_init_irq(void)
 static const char * const imx6q_dt_compat[] __initconst = {
        "fsl,imx6dl",
        "fsl,imx6q",
+       "fsl,imx6qp",
        NULL,
 };