blackfin: twi: move twi bit mask macro to twi head file
authorSonic Zhang <sonic.zhang@analog.com>
Thu, 24 Nov 2011 09:40:07 +0000 (17:40 +0800)
committerBob Liu <lliubbo@gmail.com>
Mon, 21 May 2012 06:54:21 +0000 (14:54 +0800)
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
arch/blackfin/include/asm/bfin_twi.h
arch/blackfin/mach-bf518/include/mach/defBF512.h
arch/blackfin/mach-bf527/include/mach/defBF522.h
arch/blackfin/mach-bf537/include/mach/defBF534.h
arch/blackfin/mach-bf538/include/mach/defBF538.h
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h

index e767d64..74d1023 100644 (file)
@@ -42,4 +42,74 @@ struct bfin_twi_regs {
 
 #undef __BFP
 
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                               */
+#define        CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
+#define CLKHI(y)       (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+
+/* TWI_PRESCALE Masks                                                                                                                  */
+#define        PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
+#define        TWI_ENA         0x0080  /* TWI Enable                                                                   */
+#define        SCCB            0x0200  /* SCCB Compatibility Enable                                    */
+
+/* TWI_SLAVE_CTL Masks                                                                                                                 */
+#define        SEN                     0x0001  /* Slave Enable                                                                 */
+#define        SADD_LEN        0x0002  /* Slave Address Length                                                 */
+#define        STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
+#define        NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define        GEN                     0x0010  /* General Call Address Matching Enabled                */
+
+/* TWI_SLAVE_STAT Masks                                                                                                                        */
+#define        SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL          0x0002  /* General Call Indicator                                               */
+
+/* TWI_MASTER_CTL Masks                                                                                                        */
+#define        MEN                     0x0001  /* Master Mode Enable                                           */
+#define        MADD_LEN        0x0002  /* Master Address Length                                        */
+#define        MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
+#define        FAST            0x0008  /* Use Fast Mode Timing Specs                           */
+#define        STOP            0x0010  /* Issue Stop Condition                                         */
+#define        RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
+#define        DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
+#define        SDAOVR          0x4000  /* Serial Data Override                                         */
+#define        SCLOVR          0x8000  /* Serial Clock Override                                        */
+
+/* TWI_MASTER_STAT Masks                                                                                                               */
+#define        MPROG           0x0001  /* Master Transfer In Progress                                  */
+#define        LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
+#define        ANAK            0x0004  /* Address Not Acknowledged                                             */
+#define        DNAK            0x0008  /* Data Not Acknowledged                                                */
+#define        BUFRDERR        0x0010  /* Buffer Read Error                                                    */
+#define        BUFWRERR        0x0020  /* Buffer Write Error                                                   */
+#define        SDASEN          0x0040  /* Serial Data Sense                                                    */
+#define        SCLSEN          0x0080  /* Serial Clock Sense                                                   */
+#define        BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                                */
+#define        SINIT           0x0001  /* Slave Transfer Initiated     */
+#define        SCOMP           0x0002  /* Slave Transfer Complete      */
+#define        SERR            0x0004  /* Slave Transfer Error         */
+#define        SOVF            0x0008  /* Slave Overflow                       */
+#define        MCOMP           0x0010  /* Master Transfer Complete     */
+#define        MERR            0x0020  /* Master Transfer Error        */
+#define        XMTSERV         0x0040  /* Transmit FIFO Service        */
+#define        RCVSERV         0x0080  /* Receive FIFO Service         */
+
+/* TWI_FIFO_CTRL Masks                                                                                         */
+#define        XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
+#define        RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
+#define        XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
+#define        RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
+
+/* TWI_FIFO_STAT Masks                                                                                                                 */
+#define        XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
+#define        XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
+#define        XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
+#define        XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
+
+#define        RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
+#define        RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
+#define        RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
+#define        RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
+
 #endif
index 7297040..a818bb1 100644 (file)
 #define ERR_NCOR               0x8000          /* Error Not Corrected Indicator        */
 
 
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                               */
-#define        CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)       (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                  */
-#define        PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define        TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define        SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTL Masks                                                                                                                 */
-#define        SEN                     0x0001          /* Slave Enable                                                                 */
-#define        SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define        STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define        NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define        GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                        */
-#define        SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL          0x0002          /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTL Masks                                                                                                        */
-#define        MEN                     0x0001          /* Master Mode Enable                                           */
-#define        MADD_LEN        0x0002          /* Master Address Length                                        */
-#define        MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define        FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define        STOP            0x0010          /* Issue Stop Condition                                         */
-#define        RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define        DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define        SDAOVR          0x4000          /* Serial Data Override                                         */
-#define        SCLOVR          0x8000          /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                               */
-#define        MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define        LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define        ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define        DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define        BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define        BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define        SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define        SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define        BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                                */
-#define        SINIT           0x0001          /* Slave Transfer Initiated     */
-#define        SCOMP           0x0002          /* Slave Transfer Complete      */
-#define        SERR            0x0004          /* Slave Transfer Error         */
-#define        SOVF            0x0008          /* Slave Overflow                       */
-#define        MCOMP           0x0010          /* Master Transfer Complete     */
-#define        MERR            0x0020          /* Master Transfer Error        */
-#define        XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define        RCVSERV         0x0080          /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                         */
-#define        XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define        RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define        XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define        RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                 */
-#define        XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define        XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define        XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define        XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define        RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define        RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define        RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define        RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
-
-
 /*  *******************  PIN CONTROL REGISTER MASKS  ************************/
 /* PORT_MUX Masks                                                                                                                      */
 #define        PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
index 37d353a..e8fdacb 100644 (file)
 #define ERR_NCOR               0x8000          /* Error Not Corrected Indicator        */
 
 
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                               */
-#define        CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)       (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                  */
-#define        PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define        TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define        SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTL Masks                                                                                                                 */
-#define        SEN                     0x0001          /* Slave Enable                                                                 */
-#define        SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define        STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define        NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define        GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                        */
-#define        SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL          0x0002          /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTL Masks                                                                                                        */
-#define        MEN                     0x0001          /* Master Mode Enable                                           */
-#define        MADD_LEN        0x0002          /* Master Address Length                                        */
-#define        MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define        FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define        STOP            0x0010          /* Issue Stop Condition                                         */
-#define        RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define        DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define        SDAOVR          0x4000          /* Serial Data Override                                         */
-#define        SCLOVR          0x8000          /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                               */
-#define        MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define        LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define        ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define        DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define        BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define        BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define        SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define        SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define        BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                                */
-#define        SINIT           0x0001          /* Slave Transfer Initiated     */
-#define        SCOMP           0x0002          /* Slave Transfer Complete      */
-#define        SERR            0x0004          /* Slave Transfer Error         */
-#define        SOVF            0x0008          /* Slave Overflow                       */
-#define        MCOMP           0x0010          /* Master Transfer Complete     */
-#define        MERR            0x0020          /* Master Transfer Error        */
-#define        XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define        RCVSERV         0x0080          /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                         */
-#define        XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define        RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define        XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define        RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                 */
-#define        XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define        XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define        XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define        XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define        RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define        RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define        RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define        RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
-
-
 /* Omit CAN masks from defBF534.h */
 
 /*  *******************  PIN CONTROL REGISTER MASKS  ************************/
index 4a031dd..d0deb66 100644 (file)
 #define ERR_DET                        0x4000  /* Error Detected Indicator                     */
 #define ERR_NCOR               0x8000  /* Error Not Corrected Indicator        */
 
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                               */
-#define        CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
-#define CLKHI(y)       (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                  */
-#define        PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
-#define        TWI_ENA         0x0080  /* TWI Enable                                                                   */
-#define        SCCB            0x0200  /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTL Masks                                                                                                                 */
-#define        SEN                     0x0001  /* Slave Enable                                                                 */
-#define        SADD_LEN        0x0002  /* Slave Address Length                                                 */
-#define        STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
-#define        NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define        GEN                     0x0010  /* General Call Address Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                        */
-#define        SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL          0x0002  /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTL Masks                                                                                                        */
-#define        MEN                     0x0001  /* Master Mode Enable                                           */
-#define        MADD_LEN        0x0002  /* Master Address Length                                        */
-#define        MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
-#define        FAST            0x0008  /* Use Fast Mode Timing Specs                           */
-#define        STOP            0x0010  /* Issue Stop Condition                                         */
-#define        RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
-#define        DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
-#define        SDAOVR          0x4000  /* Serial Data Override                                         */
-#define        SCLOVR          0x8000  /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                               */
-#define        MPROG           0x0001  /* Master Transfer In Progress                                  */
-#define        LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define        ANAK            0x0004  /* Address Not Acknowledged                                             */
-#define        DNAK            0x0008  /* Data Not Acknowledged                                                */
-#define        BUFRDERR        0x0010  /* Buffer Read Error                                                    */
-#define        BUFWRERR        0x0020  /* Buffer Write Error                                                   */
-#define        SDASEN          0x0040  /* Serial Data Sense                                                    */
-#define        SCLSEN          0x0080  /* Serial Clock Sense                                                   */
-#define        BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                                */
-#define        SINIT           0x0001  /* Slave Transfer Initiated     */
-#define        SCOMP           0x0002  /* Slave Transfer Complete      */
-#define        SERR            0x0004  /* Slave Transfer Error         */
-#define        SOVF            0x0008  /* Slave Overflow                       */
-#define        MCOMP           0x0010  /* Master Transfer Complete     */
-#define        MERR            0x0020  /* Master Transfer Error        */
-#define        XMTSERV         0x0040  /* Transmit FIFO Service        */
-#define        RCVSERV         0x0080  /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                         */
-#define        XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
-#define        RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
-#define        XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
-#define        RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                 */
-#define        XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
-#define        XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
-#define        XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
-#define        XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define        RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
-#define        RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
-#define        RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
-#define        RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
 
 /*  *******************  PIN CONTROL REGISTER MASKS  ************************/
 /* PORT_MUX Masks                                                                                                                      */
index d27f81d..f5aaf05 100644 (file)
 #define        SDEASE                  0x00000010 /* SDRAM EAB sticky error status - W1C */
 #define        BGSTAT                  0x00000020 /* Bus granted */
 
-
-/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
-/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);         ) */
-#ifdef _MISRA_RULES
-#define        CLKLOW(x)       ((x) & 0xFFu)           /* Periods Clock Is Held Low */
-#define        CLKHI(y)        (((y)&0xFFu)<<0x8)      /* Periods Before New Clock Low */
-#else
-#define        CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low */
-#define        CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low */
-#endif /* _MISRA_RULES */
-
-/* TWIx_PRESCALE Masks                                                          */
-#define        PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz) */
-#define        TWI_ENA         0x0080          /* TWI Enable            */
-#define        SCCB            0x0200          /* SCCB Compatibility Enable */
-
-/* TWIx_SLAVE_CTRL Masks                                                                */
-#define        SEN                     0x0001          /* Slave Enable          */
-#define        SADD_LEN        0x0002          /* Slave Address Length */
-#define        STDVAL          0x0004          /* Slave Transmit Data Valid */
-#define        NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define        GEN                     0x0010          /* General Call Adrress Matching Enabled */
-
-/* TWIx_SLAVE_STAT Masks                                                                */
-#define        SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define        GCALL           0x0002          /* General Call Indicator */
-
-/* TWIx_MASTER_CTRL Masks                                               */
-#define        MEN                     0x0001          /* Master Mode Enable */
-#define        MADD_LEN        0x0002          /* Master Address Length */
-#define        MDIR            0x0004          /* Master Transmit Direction (RX/TX*) */
-#define        FAST            0x0008          /* Use Fast Mode Timing Specs */
-#define        STOP            0x0010          /* Issue Stop Condition */
-#define        RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer */
-#define        DCNT            0x3FC0          /* Data Bytes To Transfer */
-#define        SDAOVR          0x4000          /* Serial Data Override */
-#define        SCLOVR          0x8000          /* Serial Clock Override */
-
-/* TWIx_MASTER_STAT Masks                                                       */
-#define        MPROG           0x0001          /* Master Transfer In Progress */
-#define        LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted) */
-#define        ANAK            0x0004          /* Address Not Acknowledged */
-#define        DNAK            0x0008          /* Data Not Acknowledged */
-#define        BUFRDERR        0x0010          /* Buffer Read Error */
-#define        BUFWRERR        0x0020          /* Buffer Write Error */
-#define        SDASEN          0x0040          /* Serial Data Sense */
-#define        SCLSEN          0x0080          /* Serial Clock Sense */
-#define        BUSBUSY         0x0100          /* Bus Busy Indicator */
-
-/* TWIx_INT_SRC        and TWIx_INT_ENABLE Masks */
-#define        SINIT           0x0001          /* Slave Transfer Initiated */
-#define        SCOMP           0x0002          /* Slave Transfer Complete */
-#define        SERR            0x0004          /* Slave Transfer Error */
-#define        SOVF            0x0008          /* Slave Overflow */
-#define        MCOMP           0x0010          /* Master Transfer Complete */
-#define        MERR            0x0020          /* Master Transfer Error */
-#define        XMTSERV         0x0040          /* Transmit FIFO Service */
-#define        RCVSERV         0x0080          /* Receive FIFO Service */
-
-/* TWIx_FIFO_CTL Masks                                  */
-#define        XMTFLUSH        0x0001          /* Transmit Buffer Flush */
-#define        RCVFLUSH        0x0002          /* Receive Buffer Flush */
-#define        XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length */
-#define        RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length */
-
-/* TWIx_FIFO_STAT Masks                                                                 */
-#define        XMTSTAT         0x0003          /* Transmit FIFO Status */
-#define        XMT_EMPTY       0x0000          /*              Transmit FIFO Empty */
-#define        XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write */
-#define        XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write) */
-
-#define        RCVSTAT         0x000C          /* Receive FIFO Status */
-#define        RCV_EMPTY       0x0000          /*              Receive FIFO Empty */
-#define        RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read */
-#define        RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
-
 #endif
index 0867c2b..b010230 100644 (file)
 #define                  LOW_EVEN  0xff0000   /* Lower Limit for Even Bytes (Luma) */
 #define                 HIGH_EVEN  0xff000000 /* Upper Limit for Even Bytes (Luma) */
 
-/* ************************************************ */
-/* The TWI bit masks fields are from the ADSP-BF538 */
-/* and they have not been verified as the final     */
-/* ones for the Moab processors ... bz 1/19/2007    */
-/* ************************************************ */
-
-/* Bit masks for TWIx_CONTROL */
-
-#define                  PRESCALE  0x7f       /* Prescale Value */
-#define                   TWI_ENA  0x80       /* TWI Enable */
-#define                      SCCB  0x200      /* Serial Camera Control Bus */
-
-/* Bit maskes for TWIx_CLKDIV */
-
-#define                    CLKLOW  0xff       /* Clock Low */
-#define                     CLKHI  0xff00     /* Clock High */
-
-/* Bit maskes for TWIx_SLAVE_CTL */
-
-#define                       SEN  0x1        /* Slave Enable */
-#define                    STDVAL  0x4        /* Slave Transmit Data Valid */
-#define                       NAK  0x8        /* Not Acknowledge */
-#define                       GEN  0x10       /* General Call Enable */
-
-/* Bit maskes for TWIx_SLAVE_ADDR */
-
-#define                     SADDR  0x7f       /* Slave Mode Address */
-
-/* Bit maskes for TWIx_SLAVE_STAT */
-
-#define                      SDIR  0x1        /* Slave Transfer Direction */
-#define                     GCALL  0x2        /* General Call */
-
-/* Bit maskes for TWIx_MASTER_CTL */
-
-#define                       MEN  0x1        /* Master Mode Enable */
-#define                      MDIR  0x4        /* Master Transfer Direction */
-#define                      FAST  0x8        /* Fast Mode */
-#define                      STOP  0x10       /* Issue Stop Condition */
-#define                    RSTART  0x20       /* Repeat Start */
-#define                      DCNT  0x3fc0     /* Data Transfer Count */
-#define                    SDAOVR  0x4000     /* Serial Data Override */
-#define                    SCLOVR  0x8000     /* Serial Clock Override */
-
-/* Bit maskes for TWIx_MASTER_ADDR */
-
-#define                     MADDR  0x7f       /* Master Mode Address */
-
-/* Bit maskes for TWIx_MASTER_STAT */
-
-#define                     MPROG  0x1        /* Master Transfer in Progress */
-#define                   LOSTARB  0x2        /* Lost Arbitration */
-#define                      ANAK  0x4        /* Address Not Acknowledged */
-#define                      DNAK  0x8        /* Data Not Acknowledged */
-#define                  BUFRDERR  0x10       /* Buffer Read Error */
-#define                  BUFWRERR  0x20       /* Buffer Write Error */
-#define                    SDASEN  0x40       /* Serial Data Sense */
-#define                    SCLSEN  0x80       /* Serial Clock Sense */
-#define                   BUSBUSY  0x100      /* Bus Busy */
-
-/* Bit maskes for TWIx_FIFO_CTL */
-
-#define                  XMTFLUSH  0x1        /* Transmit Buffer Flush */
-#define                  RCVFLUSH  0x2        /* Receive Buffer Flush */
-#define                 XMTINTLEN  0x4        /* Transmit Buffer Interrupt Length */
-#define                 RCVINTLEN  0x8        /* Receive Buffer Interrupt Length */
-
-/* Bit maskes for TWIx_FIFO_STAT */
-
-#define                   XMTSTAT  0x3        /* Transmit FIFO Status */
-#define                   RCVSTAT  0xc        /* Receive FIFO Status */
-
-/* Bit maskes for TWIx_INT_MASK */
-
-#define                    SINITM  0x1        /* Slave Transfer Initiated Interrupt Mask */
-#define                    SCOMPM  0x2        /* Slave Transfer Complete Interrupt Mask */
-#define                     SERRM  0x4        /* Slave Transfer Error Interrupt Mask */
-#define                     SOVFM  0x8        /* Slave Overflow Interrupt Mask */
-#define                    MCOMPM  0x10       /* Master Transfer Complete Interrupt Mask */
-#define                     MERRM  0x20       /* Master Transfer Error Interrupt Mask */
-#define                  XMTSERVM  0x40       /* Transmit FIFO Service Interrupt Mask */
-#define                  RCVSERVM  0x80       /* Receive FIFO Service Interrupt Mask */
-
-/* Bit maskes for TWIx_INT_STAT */
-
-#define                     SINIT  0x1        /* Slave Transfer Initiated */
-#define                     SCOMP  0x2        /* Slave Transfer Complete */
-#define                      SERR  0x4        /* Slave Transfer Error */
-#define                      SOVF  0x8        /* Slave Overflow */
-#define                     MCOMP  0x10       /* Master Transfer Complete */
-#define                      MERR  0x20       /* Master Transfer Error */
-#define                   XMTSERV  0x40       /* Transmit FIFO Service */
-#define                   RCVSERV  0x80       /* Receive FIFO Service */
-
-/* Bit maskes for TWIx_XMT_DATA8 */
-
-#define                  XMTDATA8  0xff       /* Transmit FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_XMT_DATA16 */
-
-#define                 XMTDATA16  0xffff     /* Transmit FIFO 16-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA8 */
-
-#define                  RCVDATA8  0xff       /* Receive FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA16 */
-
-#define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
 
 /* ******************************************* */
 /*     MULTI BIT MACRO ENUMERATIONS            */