{
PMSMBus *s = opaque;
- SMBUS_DPRINTF("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
+ SMBUS_DPRINTF("SMB writeb port=0x%04" HWADDR_PRIx
+ " val=0x%02" PRIx64 "\n", addr, val);
switch(addr) {
case SMBHSTSTS:
s->smb_stat = (~(val & 0xff)) & s->smb_stat;
val = 0;
break;
}
- SMBUS_DPRINTF("SMB readb port=0x%04x val=0x%02x\n", addr, val);
+ SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n", addr, val);
return val;
}
Port92State *s = opaque;
int oldval = s->outport;
- DPRINTF("port92: write 0x%02x\n", val);
+ DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
s->outport = val;
qemu_set_irq(*s->a20_out, (val >> 1) & 1);
if ((val & 1) && !(oldval & 1)) {
{
KBDState *s = opaque;
- DPRINTF("kbd: write cmd=0x%02x\n", val);
+ DPRINTF("kbd: write cmd=0x%02" PRIx64 "\n", val);
/* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
* low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
{
KBDState *s = opaque;
- DPRINTF("kbd: write data=0x%02x\n", val);
+ DPRINTF("kbd: write data=0x%02" PRIx64 "\n", val);
switch(s->write_cmd) {
case 0:
ret = s->imr;
}
}
- DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
+ DPRINTF("read: addr=0x%02" HWADDR_PRIx " val=0x%02x\n", addr, ret);
return ret;
}
{
APMState *apm = opaque;
addr &= 1;
- APM_DPRINTF("apm_ioport_writeb addr=0x%x val=0x%02x\n", addr, val);
+ APM_DPRINTF("apm_ioport_writeb addr=0x%" HWADDR_PRIx
+ " val=0x%02" PRIx64 "\n", addr, val);
if (addr == 0) {
apm->apmc = val;
} else {
val = apm->apms;
}
- APM_DPRINTF("apm_ioport_readb addr=0x%x val=0x%02x\n", addr, val);
+ APM_DPRINTF("apm_ioport_readb addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, val);
return val;
}
if ((addr & 1) == 0) {
s->cmos_index = data & 0x7f;
} else {
- CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
+ CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
s->cmos_index, data);
switch(s->cmos_index) {
case RTC_SECONDS_ALARM: