Cleanup of some hardcoded values in OTM HDMI driver.
authorGandhimathi Anand <gandhimathi.anand@intel.com>
Tue, 14 Feb 2012 22:06:41 +0000 (14:06 -0800)
committerMarkus Lehtonen <markus.lehtonen@linux.intel.com>
Tue, 3 Jul 2012 09:30:11 +0000 (12:30 +0300)
Removed some hardcode values and replace with meaningful macros.

OTM_HDMI: r3001

Signed-off-by: Arun Kannan <arun.kannan@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
drivers/staging/mrst/drv/otm_hdmi/ipil/common/ipil_internal.h
drivers/staging/mrst/drv/otm_hdmi/ipil/common/otm_ipil_main.c
drivers/staging/mrst/drv/otm_hdmi/ipil/specific/include/ips_hdmi.h

index 9dbd3d2..5b3b74c 100644 (file)
 #define IPIL_TIMING_FLAG_PVSYNC        (1<<2)
 #define IPIL_TIMING_FLAG_NVSYNC        (1<<3)
 
+#define IPIL_HSYNC_POLARITY_MASK IPS_HSYNC_POLARITY_MASK
+#define IPIL_VSYNC_POLARITY_MASK IPS_VSYNC_POLARITY_MASK
+#define CLEARBITS(val, mask) (val & (~mask))
+#define SETBITS(val, mask)  (val | mask)
 struct ipil_clock_t {
        int dot;
        int m;
index f85b771..62c70c6 100644 (file)
@@ -765,10 +765,14 @@ otm_hdmi_ret_t ipil_hdmi_enc_mode_set(hdmi_device_t *dev,
                                                adjusted_mode->height,
                                                phsync ? '+' : '-',
                                                pvsync ? '+' : '-');
-       /* TODO: define macros for hard coded values */
-       hdmib &= ~0x18; /* clean bit 3 and 4 */
-       hdmib |= phsync ? 0x8  : 0x0; /* bit 3 */
-       hdmib |= pvsync ? 0x10 : 0x0; /* bit 4 */
+       if (phsync)
+               hdmib = SETBITS(hdmib, IPIL_HSYNC_POLARITY_MASK);
+       else
+               hdmib = CLEARBITS(hdmib, IPIL_HSYNC_POLARITY_MASK);
+       if (pvsync)
+               hdmib = SETBITS(hdmib, IPIL_VSYNC_POLARITY_MASK);
+       else
+               hdmib = CLEARBITS(hdmib, IPIL_VSYNC_POLARITY_MASK);
 
        hdmi_phy_misc = hdmi_read32(IPIL_HDMIPHYMISCCTL) &
                                        ~IPIL_HDMI_PHY_POWER_DOWN;
index 1422bed..a4f254c 100644 (file)
 #define IPS_HDMIB_CONTROL    (0x61140)
 #define IPS_PFIT_ENABLE                (1 << 31)
 
+/* HSYNC and VSYNC Polarity Mask Bits */
+#define IPS_HSYNC_POLARITY_MASK (1 << 3)
+#define IPS_VSYNC_POLARITY_MASK (1 << 4)
+
 otm_hdmi_ret_t ips_hdmi_decide_I2C_HW(hdmi_context_t *ctx);
 
 otm_hdmi_ret_t ips_hdmi_general_5V_enable(hdmi_device_t *dev);