[RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where...

This avoids being dependent on SimplifyDemandedBits having cleared
those bits.

It could make sense to teach SimplifyDemandedBits to keep all
lower bits 1 in an AND mask when possible. This could be
implemented with slli+srli in the general case rather than
needing to materialize the constant.

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 078ed1b..2198b27 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -871,7 +871,7 @@ bool RISCVDAGToDAGISel::MatchSLLIUW(SDNode *N) const {
 
   // Immediate range should be enforced by uimm5 predicate.
   assert(VC2 < 32 && "Unexpected immediate");
-  return VC1 == ((uint64_t)0xFFFFFFFF << VC2);
+  return (VC1 >> VC2) == UINT64_C(0xFFFFFFFF);
 }
 
 bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {