This avoids being dependent on SimplifyDemandedBits having cleared
those bits.
It could make sense to teach SimplifyDemandedBits to keep all
lower bits 1 in an AND mask when possible. This could be
implemented with slli+srli in the general case rather than
needing to materialize the constant.
// Immediate range should be enforced by uimm5 predicate.
assert(VC2 < 32 && "Unexpected immediate");
- return VC1 == ((uint64_t)0xFFFFFFFF << VC2);
+ return (VC1 >> VC2) == UINT64_C(0xFFFFFFFF);
}
bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {