ARM: dts: Configure interconnect target module for dra7 hdmi

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module and drop "ti,hwmods" peroperty as this module is a child node
of dispc and has no dependencies to to legacy platform data.

Cc: Jyri Sarha <jsarha@ti.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 594b53a..2849bed 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -767,21 +767,38 @@
                                        };
                                };
 
-                               hdmi: encoder@40000 {
-                                       compatible = "ti,dra7-hdmi";
-                                       reg = <0x40000 0x200>,
-                                             <0x40200 0x80>,
-                                             <0x40300 0x80>,
-                                             <0x60000 0x19000>;
-                                       reg-names = "wp", "pll", "phy", "core";
-                                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-                                       status = "disabled";
-                                       ti,hwmods = "dss_hdmi";
-                                       clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
-                                                <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
-                                       clock-names = "fck", "sys_clk";
-                                       dmas = <&sdma_xbar 76>;
-                                       dma-names = "audio_tx";
+                               target-module@40000 {
+                                       compatible = "ti,sysc-omap4", "ti,sysc";
+                                       reg = <0x40000 0x4>,
+                                             <0x40010 0x4>;
+                                       reg-names = "rev", "sysc";
+                                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                                       <SYSC_IDLE_NO>,
+                                                       <SYSC_IDLE_SMART>,
+                                                       <SYSC_IDLE_SMART_WKUP>;
+                                       ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
+                                       clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
+                                                <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
+                                       clock-names = "fck", "dss_clk";
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+                                       ranges = <0 0x40000 0x40000>;
+
+                                       hdmi: encoder@0 {
+                                               compatible = "ti,dra7-hdmi";
+                                               reg = <0 0x200>,
+                                                     <0x200 0x80>,
+                                                     <0x300 0x80>,
+                                                     <0x20000 0x19000>;
+                                               reg-names = "wp", "pll", "phy", "core";
+                                               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                                               status = "disabled";
+                                               clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
+                                                        <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
+                                               clock-names = "fck", "sys_clk";
+                                               dmas = <&sdma_xbar 76>;
+                                               dma-names = "audio_tx";
+                                       };
                                };
                        };
                };