return ScratchRegs;
}
+const MCPhysReg *AArch64TargetLowering::getRoundingControlRegisters() const {
+ static const MCPhysReg RCRegs[] = {AArch64::FPCR, 0};
+ return RCRegs;
+}
+
bool
AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
CombineLevel Level) const {
CodeGenOpt::Level OptLevel) const override;
const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
+ const MCPhysReg *getRoundingControlRegisters() const override;
/// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool isDesirableToCommuteWithShift(const SDNode *N,
--- /dev/null
+; RUN: llc -mtriple aarch64-none-linux-gnu -stop-after=finalize-isel %s -o - | FileCheck %s
+
+define float @func_02(float %x, float %y) strictfp nounwind {
+ %call = call float @func_01(float %x) strictfp
+ %res = call float @llvm.experimental.constrained.fadd.f32(float %call, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore") strictfp
+ ret float %res
+}
+; CHECK-LABEL: name: func_02
+; CHECK: BL @func_01, {{.*}}, implicit-def $fpcr
+
+
+declare float @func_01(float)
+declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)