drm/amdgpu: configure navy_flounder gfx according to gfx 10.3

The gfx version of navy_flounder is 10.3, identical to
sienna_cichlid, follow the way of sienna_cichlid.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fd3175e..b289486 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5732,6 +5732,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
        WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
                                    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
                WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -5864,6 +5865,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
        if (enable) {
                switch (adev->asic_type) {
                case CHIP_SIENNA_CICHLID:
+               case CHIP_NAVY_FLOUNDER:
                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
                        break;
                default:
@@ -5873,6 +5875,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
        } else {
                switch (adev->asic_type) {
                case CHIP_SIENNA_CICHLID:
+               case CHIP_NAVY_FLOUNDER:
                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
                                     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
                                      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -5966,6 +5969,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
        /* tell RLC which is KIQ queue */
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
                tmp &= 0xffffff00;
                tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -6669,6 +6673,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
         * has been remapped to mmVGT_ESGS_RING_SIZE */
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
                WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
                WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
@@ -6707,6 +6712,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -6997,6 +7003,7 @@ static int gfx_v10_0_soft_reset(void *handle)
        tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
                        grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
                                                        GRBM_SOFT_RESET,
@@ -7148,6 +7155,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 
                /* wait for RLC_SAFE_MODE */
@@ -7179,6 +7187,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
        data = RLC_SAFE_MODE__CMD_MASK;
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
                break;
        default: