ARM: keystone2: add K2L device hardware definitions

This patch adds hardware definitions specific to Keystone II
Lamar (K2L) SoC.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 43c2c42..2db806c 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -10,8 +10,6 @@
 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
 #define __ASM_ARCH_HARDWARE_K2HK_H
 
-#define KS2_MISC_CTRL                  (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
 #define KS2_ARM_PLL_EN                 BIT(13)
 
 /* PA SS Registers */

diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
new file mode 100644 (file)
index 0000000..3402d0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -0,0 +1,74 @@
+/*
+ * K2L: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2L_H
+#define __ASM_ARCH_HARDWARE_K2L_H
+
+#define KS2_ARM_PLL_EN                 BIT(13)
+
+/* PA SS Registers */
+#define KS2_PASS_BASE                  0x26000000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD                   0
+#define KS2_LPSC_DFE_IQN_SYS           1
+#define KS2_LPSC_USB                   2
+#define KS2_LPSC_EMIF25_SPI            3
+#define KS2_LPSC_TSIP                   4
+#define KS2_LPSC_DEBUGSS_TRC           5
+#define KS2_LPSC_TETB_TRC              6
+#define KS2_LPSC_PKTPROC               7
+#define KS2_LPSC_PA                    KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII                 8
+#define KS2_LPSC_CPGMAC                        KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO                        9
+#define KS2_LPSC_PCIE0                 10
+#define KS2_LPSC_PCIE1                 11
+#define KS2_LPSC_JESD_MISC             12
+#define KS2_LPSC_CHIP_SRSS             13
+#define KS2_LPSC_MSMC                  14
+#define KS2_LPSC_GEM_1                 16
+#define KS2_LPSC_GEM_2                 17
+#define KS2_LPSC_GEM_3                 18
+#define KS2_LPSC_EMIF4F_DDR3           23
+#define KS2_LPSC_TAC                   25
+#define KS2_LPSC_RAC                   26
+#define KS2_LPSC_DDUC4X_CFR2X_BB       27
+#define KS2_LPSC_FFTC_A                        28
+#define KS2_LPSC_OSR                   34
+#define KS2_LPSC_TCP3D_0               35
+#define KS2_LPSC_TCP3D_1               37
+#define KS2_LPSC_VCP2X4_A              39
+#define KS2_LPSC_VCP2X4_B              40
+#define KS2_LPSC_VCP2X4_C              41
+#define KS2_LPSC_VCP2X4_D              42
+#define KS2_LPSC_BCP                   47
+#define KS2_LPSC_DPD4X                 48
+#define KS2_LPSC_FFTC_B                        49
+#define KS2_LPSC_IQN_AIL               50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM      0x0D3
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM     0x01D
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS                   4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE       0x26186000
+#define KS2_NETCP_PDMA_TX_BASE         0x26187000
+#define KS2_NETCP_PDMA_TX_CH_NUM       21
+#define KS2_NETCP_PDMA_RX_BASE         0x26188000
+#define KS2_NETCP_PDMA_RX_CH_NUM       91
+#define KS2_NETCP_PDMA_SCHED_BASE      0x26186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE    0x26189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM     96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE    896
+
+#endif /* __ASM_ARCH_HARDWARE_K2L_H */

diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index c1642a5..adae69e 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -143,6 +143,7 @@ typedef volatile unsigned int   *dv_reg_p;
 /* Device speed */
 #define KS2_REV1_DEVSPEED              (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
 #define KS2_EFUSE_BOOTROM              (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+#define KS2_MISC_CTRL                  (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
 
 /* Queue manager */
 #define KS2_QM_BASE_ADDRESS            0x23a80000
@@ -177,6 +178,10 @@ typedef volatile unsigned int   *dv_reg_p;
 #include <asm/arch/hardware-k2e.h>
 #endif
 
+#ifdef CONFIG_SOC_K2L
+#include <asm/arch/hardware-k2l.h>
+#endif
+
 #ifndef __ASSEMBLY__
 static inline int cpu_is_k2hk(void)
 {
@@ -194,6 +199,14 @@ static inline int cpu_is_k2e(void)
        return (part_no == 0xb9a6) ? 1 : 0;
 }
 
+static inline int cpu_is_k2l(void)
+{
+       unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
+       unsigned int part_no    = (jtag_id >> 12) & 0xffff;
+
+       return (part_no == 0xb9a7) ? 1 : 0;
+}
+
 static inline int cpu_revision(void)
 {
        unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);