drm/i915/gen12: Apply recommended L3 hashing mask

The TGL/RKL/DG1/ADL performance tuning guide suggests programming a
literal value of 0x2FC0100F for this register.  The register's hardware
default value is 0x2FC0108F, so this translates to just clearing one
bit.

Take this opportunity to also clean up the register definition and
re-write its existing bits/fields in the preferred notation.

Bspec: 31870
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221201222210.344152-1-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 9931882..d255c84 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -957,10 +957,11 @@
 #define   GEN7_DISABLE_SAMPLER_PREFETCH                (1 << 30)
 
 #define GEN8_GARBCNTL                          _MMIO(0xb004)
-#define   GEN9_GAPS_TSV_CREDIT_DISABLE         (1 << 7)
-#define   GEN11_ARBITRATION_PRIO_ORDER_MASK    (0x3f << 22)
-#define   GEN11_HASH_CTRL_EXCL_MASK            (0x7f << 0)
-#define   GEN11_HASH_CTRL_EXCL_BIT0            (1 << 0)
+#define   GEN11_ARBITRATION_PRIO_ORDER_MASK    REG_GENMASK(27, 22)
+#define   GEN12_BUS_HASH_CTL_BIT_EXC           REG_BIT(7)
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE         REG_BIT(7)
+#define   GEN11_HASH_CTRL_EXCL_MASK            REG_GENMASK(6, 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0            REG_FIELD_PREP(GEN11_HASH_CTRL_EXCL_MASK, 0x1)
 
 #define GEN9_SCRATCH_LNCF1                     _MMIO(0xb008)
 #define   GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE      REG_BIT(0)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ff63b38..38746a7 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2936,6 +2936,9 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
        if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
                wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
                                        THREAD_EX_ARB_MODE_RR_AFTER_DEP);
+
+       if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+               wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
 }
 
 /*