powerpc/ptrace: Enable NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR

This patch enables support for all three TM checkpointed SPR
states related ELF core note  NT_PPC_TM_CTAR, NT_PPC_TM_CPPR,
NT_PPC_TM_CDSCR based ptrace requests through PTRACE_GETREGSET,
PTRACE_SETREGSET calls. This is achieved through adding three
new register sets REGSET_TM_CTAR, REGSET_TM_CPPR and
REGSET_TM_CDSCR in powerpc corresponding to the ELF core note
sections added. It implements the get, set and active functions
for all these new register sets added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index f654224..a81e2d7 100644 (file)
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1542,6 +1542,151 @@ static int tm_spr_set(struct task_struct *target,
                                 2 * sizeof(u64), 3 * sizeof(u64));
        return ret;
 }
+
+static int tm_tar_active(struct task_struct *target,
+                        const struct user_regset *regset)
+{
+       if (!cpu_has_feature(CPU_FTR_TM))
+               return -ENODEV;
+
+       if (MSR_TM_ACTIVE(target->thread.regs->msr))
+               return regset->n;
+
+       return 0;
+}
+
+static int tm_tar_get(struct task_struct *target,
+                     const struct user_regset *regset,
+                     unsigned int pos, unsigned int count,
+                     void *kbuf, void __user *ubuf)
+{
+       int ret;
+
+       if (!cpu_has_feature(CPU_FTR_TM))
+               return -ENODEV;
+
+       if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+               return -ENODATA;
+
+       ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                               &target->thread.tm_tar, 0, sizeof(u64));
+       return ret;
+}
+
+static int tm_tar_set(struct task_struct *target,
+                     const struct user_regset *regset,
+                     unsigned int pos, unsigned int count,
+                     const void *kbuf, const void __user *ubuf)
+{
+       int ret;
+
+       if (!cpu_has_feature(CPU_FTR_TM))
+               return -ENODEV;
+
+       if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+               return -ENODATA;
+
+       ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                               &target->thread.tm_tar, 0, sizeof(u64));
+       return ret;
+}
+
+static int tm_ppr_active(struct task_struct *target,
+                        const struct user_regset *regset)
+{
+       if (!cpu_has_feature(CPU_FTR_TM))
+               return -ENODEV;
+
+       if (MSR_TM_ACTIVE(target->thread.regs->msr))
+               return regset->n;
+
+       return 0;
+}
+
+
+static int tm_ppr_get(struct task_struct *target,
+                     const struct user_regset *regset,
+                     unsigned int pos, unsigned int count,
+                     void *kbuf, void __user *ubuf)
+{
+       int ret;
+
+       if (!cpu_has_feature(CPU_FTR_TM))
+               return -ENODEV;
+
+       if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+               return -ENODATA;
+
+       ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                               &target->thread.tm_ppr, 0, sizeof(u64));
+       return ret;
+}
+
+static int tm_ppr_set(struct task_struct *target,
+                     const struct user_regset *regset,
+                     unsigned int pos, unsigned int count,
+                     const void *kbuf, const void __user *ubuf)
+{
+       int ret;
+
+       if (!cpu_has_feature(CPU_FTR_TM))
+               return -ENODEV;
+
+       if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+               return -ENODATA;
+
+       ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                               &target->thread.tm_ppr, 0, sizeof(u64));
+       return ret;
+}
+
+static int tm_dscr_active(struct task_struct *target,
+                        const struct user_regset *regset)
+{
+       if (!cpu_has_feature(CPU_FTR_TM))
+               return -ENODEV;
+
+       if (MSR_TM_ACTIVE(target->thread.regs->msr))
+               return regset->n;
+
+       return 0;
+}
+
+static int tm_dscr_get(struct task_struct *target,
+                     const struct user_regset *regset,
+                     unsigned int pos, unsigned int count,
+                     void *kbuf, void __user *ubuf)
+{
+       int ret;
+
+       if (!cpu_has_feature(CPU_FTR_TM))
+               return -ENODEV;
+
+       if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+               return -ENODATA;
+
+       ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                               &target->thread.tm_dscr, 0, sizeof(u64));
+       return ret;
+}
+
+static int tm_dscr_set(struct task_struct *target,
+                     const struct user_regset *regset,
+                     unsigned int pos, unsigned int count,
+                     const void *kbuf, const void __user *ubuf)
+{
+       int ret;
+
+       if (!cpu_has_feature(CPU_FTR_TM))
+               return -ENODEV;
+
+       if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+               return -ENODATA;
+
+       ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                               &target->thread.tm_dscr, 0, sizeof(u64));
+       return ret;
+}
 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 
 /*
@@ -1565,6 +1710,9 @@ enum powerpc_regset {
        REGSET_TM_CVMX,         /* TM checkpointed VMX registers */
        REGSET_TM_CVSX,         /* TM checkpointed VSX registers */
        REGSET_TM_SPR,          /* TM specific SPR registers */
+       REGSET_TM_CTAR,         /* TM checkpointed TAR register */
+       REGSET_TM_CPPR,         /* TM checkpointed PPR register */
+       REGSET_TM_CDSCR,        /* TM checkpointed DSCR register */
 #endif
 };
 
@@ -1626,6 +1774,21 @@ static const struct user_regset native_regsets[] = {
                .size = sizeof(u64), .align = sizeof(u64),
                .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
        },
+       [REGSET_TM_CTAR] = {
+               .core_note_type = NT_PPC_TM_CTAR, .n = 1,
+               .size = sizeof(u64), .align = sizeof(u64),
+               .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
+       },
+       [REGSET_TM_CPPR] = {
+               .core_note_type = NT_PPC_TM_CPPR, .n = 1,
+               .size = sizeof(u64), .align = sizeof(u64),
+               .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
+       },
+       [REGSET_TM_CDSCR] = {
+               .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
+               .size = sizeof(u64), .align = sizeof(u64),
+               .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
+       },
 #endif
 };
 
@@ -1878,6 +2041,21 @@ static const struct user_regset compat_regsets[] = {
                .size = sizeof(u64), .align = sizeof(u64),
                .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
        },
+       [REGSET_TM_CTAR] = {
+               .core_note_type = NT_PPC_TM_CTAR, .n = 1,
+               .size = sizeof(u64), .align = sizeof(u64),
+               .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
+       },
+       [REGSET_TM_CPPR] = {
+               .core_note_type = NT_PPC_TM_CPPR, .n = 1,
+               .size = sizeof(u64), .align = sizeof(u64),
+               .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
+       },
+       [REGSET_TM_CDSCR] = {
+               .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
+               .size = sizeof(u64), .align = sizeof(u64),
+               .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
+       },
 #endif
 };