+++ /dev/null
---------------------------------------------------------------------------
- = Zynq UltraScale+ MPSoC and Versal reset driver binding =
---------------------------------------------------------------------------
-The Zynq UltraScale+ MPSoC and Versal has several different resets.
-
-See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
-about zynqmp resets.
-
-Please also refer to reset.txt in this directory for common reset
-controller binding usage.
-
-Required Properties:
-- compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
- "xlnx,versal-reset" for Versal platform
-- #reset-cells: Specifies the number of cells needed to encode reset
- line, should be 1
-
--------
-Example
--------
-
-firmware {
- zynqmp_firmware: zynqmp-firmware {
- compatible = "xlnx,zynqmp-firmware";
- method = "smc";
-
- zynqmp_reset: reset-controller {
- compatible = "xlnx,zynqmp-reset";
- #reset-cells = <1>;
- };
- };
-};
-
-Specifying reset lines connected to IP modules
-==============================================
-
-Device nodes that need access to reset lines should
-specify them as a reset phandle in their corresponding node as
-specified in reset.txt.
-
-For list of all valid reset indices for Zynq UltraScale+ MPSoC see
-<dt-bindings/reset/xlnx-zynqmp-resets.h>
-For list of all valid reset indices for Versal see
-<dt-bindings/reset/xlnx-versal-resets.h>
-
-Example:
-
-serdes: zynqmp_phy@fd400000 {
- ...
-
- resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
- reset-names = "sata_rst";
-
- ...
-};
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Zynq UltraScale+ MPSoC and Versal reset
+
+maintainers:
+ - Piyush Mehta <piyush.mehta@amd.com>
+
+description: |
+ The Zynq UltraScale+ MPSoC and Versal has several different resets.
+
+ The PS reset subsystem is responsible for handling the external reset
+ input to the device and that all internal reset requirements are met
+ for the system (as a whole) and for the functional units.
+
+ Please also refer to reset.txt in this directory for common reset
+ controller binding usage. Device nodes that need access to reset
+ lines should specify them as a reset phandle in their corresponding
+ node as specified in reset.txt.
+
+ For list of all valid reset indices for Zynq UltraScale+ MPSoC
+ <dt-bindings/reset/xlnx-zynqmp-resets.h>
+
+ For list of all valid reset indices for Versal
+ <dt-bindings/reset/xlnx-versal-resets.h>
+
+properties:
+ compatible:
+ enum:
+ - xlnx,zynqmp-reset
+ - xlnx,versal-reset
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ zynqmp_reset: reset-controller {
+ compatible = "xlnx,zynqmp-reset";
+ #reset-cells = <1>;
+ };
+
+...