* ppc-tdep.h (struct gdbarch_tdep): Change definition of

ppc_fp0_regnum and ppc_fpscr_regnum: if they are -1, then this
processor variant lacks those registers.
(ppc_floating_point_unit_p): Change description to make it clear
that this returns info about the ISA, not the ABI.
* rs6000-tdep.c (ppc_floating_point_unit_p): Decide whether to
return true or false by checking tdep->ppc_fp0_regnum and
tdep->ppc_fpscr_regnum.  The original code replicated the BFD
arch/mach switching done in rs6000_gdbarch_init; it's better to
keep that logic there, and just check the results here.
(rs6000_gdbarch_init): On the E500, set tdep->ppc_fp0_regnum and
tdep->ppc_fpscr_regnum to -1 to indicate that we have no
floating-point registers.
(ppc_supply_fpregset, ppc_collect_fpregset)
(rs6000_push_dummy_call, rs6000_extract_return_value)
(rs6000_store_return_value): Assert that we have floating-point
registers.
(rs6000_dwarf2_stab_reg_to_regnum): Add FIXME.
(rs6000_frame_cache): Don't note the locations at which
floating-point registers were saved if we have no fprs.
* aix-thread.c (supply_fprs, fill_fprs): Assert that we have FP
registers.
(fetch_regs_user_thread, fetch_regs_kernel_thread)
(store_regs_user_thread, store_regs_kernel_thread): Only call
supply_fprs / fill_fprs if we actually have floating-point
registers.
(special_register_p): Check ppc_fpscr_regnum before matching
against it.
(supply_sprs64, supply_sprs32, fill_sprs64, fill_sprs32): Don't
supply / collect fpscr if we don't have it.
* ppc-bdm.c: #include "gdb_assert.h".
(bdm_ppc_fetch_registers, bdm_ppc_store_registers): Assert that we
have floating-point registers, since I can't test this code on
FP-free systems to adapt it.
* ppc-linux-nat.c (ppc_register_u_addr): Don't match against the
fpscr and floating point register numbers if they don't exist.
(fetch_register): Assert that we have floating-point registers
before we reach the code that handles them.
(store_register): Same.  And use tdep instead of calling
gdbarch_tdep again.
(fill_fpregset): Don't try to collect FP registers and fpscr if we
don't have them.
(ppc_linux_sigtramp_cache): Don't record the saved locations of
fprs and fpscr if we don't have them.
(ppc_linux_supply_fpregset): Don't supply fp regs and fpscr if we
don't have them.
* ppcnbsd-nat.c: #include "gdb_assert.h".
(getfpregs_supplies): Assert that we have floating-point registers.
* ppcnbsd-tdep.c (ppcnbsd_supply_fpreg, ppcnbsd_fill_fpreg): Same.
* ppcobsd-tdep.c: #include "gdb_assert.h".
(ppcobsd_supply_gregset, ppcobsd_collect_gregset): Assert that we
have floating-point registers.
* rs6000-nat.c (regmap): Don't match against the fpscr and
floating point register numbers if they don't exist.
(fetch_inferior_registers, store_inferior_registers,
fetch_core_registers): Only fetch / store / supply the
floating-point registers and the fpscr if we have them.
* Makefile.in (ppc-bdm.o, ppc-linux-nat.o, ppcnbsd-nat.o)
(ppcobsd-tdep.o): Update dependencies.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 654d11b..af504aa 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,5 +1,65 @@
 2004-05-10  Jim Blandy  <jimb@redhat.com>
 
+       * ppc-tdep.h (struct gdbarch_tdep): Change definition of
+       ppc_fp0_regnum and ppc_fpscr_regnum: if they are -1, then this
+       processor variant lacks those registers.
+       (ppc_floating_point_unit_p): Change description to make it clear
+       that this returns info about the ISA, not the ABI.
+       * rs6000-tdep.c (ppc_floating_point_unit_p): Decide whether to
+       return true or false by checking tdep->ppc_fp0_regnum and
+       tdep->ppc_fpscr_regnum.  The original code replicated the BFD
+       arch/mach switching done in rs6000_gdbarch_init; it's better to
+       keep that logic there, and just check the results here.
+       (rs6000_gdbarch_init): On the E500, set tdep->ppc_fp0_regnum and
+       tdep->ppc_fpscr_regnum to -1 to indicate that we have no
+       floating-point registers.
+       (ppc_supply_fpregset, ppc_collect_fpregset)
+       (rs6000_push_dummy_call, rs6000_extract_return_value)
+       (rs6000_store_return_value): Assert that we have floating-point
+       registers.
+       (rs6000_dwarf2_stab_reg_to_regnum): Add FIXME.
+       (rs6000_frame_cache): Don't note the locations at which
+       floating-point registers were saved if we have no fprs.
+       * aix-thread.c (supply_fprs, fill_fprs): Assert that we have FP
+       registers.
+       (fetch_regs_user_thread, fetch_regs_kernel_thread)
+       (store_regs_user_thread, store_regs_kernel_thread): Only call
+       supply_fprs / fill_fprs if we actually have floating-point
+       registers.
+       (special_register_p): Check ppc_fpscr_regnum before matching
+       against it.
+       (supply_sprs64, supply_sprs32, fill_sprs64, fill_sprs32): Don't
+       supply / collect fpscr if we don't have it.
+       * ppc-bdm.c: #include "gdb_assert.h".
+       (bdm_ppc_fetch_registers, bdm_ppc_store_registers): Assert that we
+       have floating-point registers, since I can't test this code on
+       FP-free systems to adapt it.
+       * ppc-linux-nat.c (ppc_register_u_addr): Don't match against the
+       fpscr and floating point register numbers if they don't exist.
+       (fetch_register): Assert that we have floating-point registers
+       before we reach the code that handles them.
+       (store_register): Same.  And use tdep instead of calling
+       gdbarch_tdep again.
+       (fill_fpregset): Don't try to collect FP registers and fpscr if we
+       don't have them.
+       (ppc_linux_sigtramp_cache): Don't record the saved locations of
+       fprs and fpscr if we don't have them.
+       (ppc_linux_supply_fpregset): Don't supply fp regs and fpscr if we
+       don't have them.
+       * ppcnbsd-nat.c: #include "gdb_assert.h".
+       (getfpregs_supplies): Assert that we have floating-point registers.
+       * ppcnbsd-tdep.c (ppcnbsd_supply_fpreg, ppcnbsd_fill_fpreg): Same.
+       * ppcobsd-tdep.c: #include "gdb_assert.h".
+       (ppcobsd_supply_gregset, ppcobsd_collect_gregset): Assert that we
+       have floating-point registers.
+       * rs6000-nat.c (regmap): Don't match against the fpscr and
+       floating point register numbers if they don't exist.
+       (fetch_inferior_registers, store_inferior_registers,
+       fetch_core_registers): Only fetch / store / supply the
+       floating-point registers and the fpscr if we have them.
+       * Makefile.in (ppc-bdm.o, ppc-linux-nat.o, ppcnbsd-nat.o)
+       (ppcobsd-tdep.o): Update dependencies.
+       
        * rs6000-tdep.c (ppc_collect_gregset): When regnum == -1, do
        collect all the gprs.
 

diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 4497fa8..151cb1d 100644 (file)
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -2148,26 +2148,26 @@ p-lang.o: p-lang.c $(defs_h) $(gdb_string_h) $(symtab_h) $(gdbtypes_h) \
 ppc-bdm.o: ppc-bdm.c $(defs_h) $(gdbcore_h) $(gdb_string_h) $(frame_h) \
        $(inferior_h) $(bfd_h) $(symfile_h) $(target_h) $(gdbcmd_h) \
        $(objfiles_h) $(gdb_stabs_h) $(serial_h) $(ocd_h) $(ppc_tdep_h) \
-       $(regcache_h)
+       $(regcache_h) $(gdb_assert_h)
 ppcbug-rom.o: ppcbug-rom.c $(defs_h) $(gdbcore_h) $(target_h) $(monitor_h) \
        $(serial_h) $(regcache_h)
 ppc-linux-nat.o: ppc-linux-nat.c $(defs_h) $(gdb_string_h) $(frame_h) \
-       $(inferior_h) $(gdbcore_h) $(regcache_h) $(gdb_wait_h) $(gregset_h) \
-       $(ppc_tdep_h)
+       $(inferior_h) $(gdbcore_h) $(regcache_h) $(gdb_assert_h) \
+       $(gdb_wait_h) $(gregset_h) $(ppc_tdep_h)
 ppc-linux-tdep.o: ppc-linux-tdep.c $(defs_h) $(frame_h) $(inferior_h) \
        $(symtab_h) $(target_h) $(gdbcore_h) $(gdbcmd_h) $(symfile_h) \
        $(objfiles_h) $(regcache_h) $(value_h) $(osabi_h) $(regset_h) \
        $(solib_svr4_h) $(ppc_tdep_h) $(trad_frame_h) $(frame_unwind_h)
 ppcnbsd-nat.o: ppcnbsd-nat.c $(defs_h) $(inferior_h) $(ppc_tdep_h) \
-       $(ppcnbsd_tdep_h)
+       $(ppcnbsd_tdep_h) $(gdb_assert_h)
 ppcnbsd-tdep.o: ppcnbsd-tdep.c $(defs_h) $(gdbcore_h) $(regcache_h) \
        $(target_h) $(breakpoint_h) $(value_h) $(osabi_h) $(ppc_tdep_h) \
        $(ppcnbsd_tdep_h) $(nbsd_tdep_h) $(solib_svr4_h)
 ppcobsd-nat.o: ppcobsd-nat.c $(defs_h) $(inferior_h) $(regcache_h) \
        $(ppc_tdep_h) $(ppcobsd_tdep_h)
 ppcobsd-tdep.o: ppcobsd-tdep.c $(defs_h) $(arch_utils_h) $(osabi_h) \
-       $(regcache_h) $(regset_h) $(gdb_string_h) $(ppc_tdep_h) \
-       $(ppcobsd_tdep_h) $(solib_svr4_h)
+       $(regcache_h) $(regset_h) $(gdb_assert_h) $(gdb_string_h) \
+        $(ppc_tdep_h) $(ppcobsd_tdep_h) $(solib_svr4_h)
 ppc-sysv-tdep.o: ppc-sysv-tdep.c $(defs_h) $(gdbcore_h) $(inferior_h) \
        $(regcache_h) $(value_h) $(gdb_string_h) $(gdb_assert_h) \
        $(ppc_tdep_h) $(target_h) $(objfiles_h)

diff --git a/gdb/aix-thread.c b/gdb/aix-thread.c
index 2f79071..dcaa3fb 100644 (file)
--- a/gdb/aix-thread.c
+++ b/gdb/aix-thread.c
@@ -1023,6 +1023,10 @@ supply_fprs (double *vals)
   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
   int regno;
 
+  /* This function should never be called on architectures without
+     floating-point registers.  */
+  gdb_assert (ppc_floating_point_p (current_gdbarch));
+
   for (regno = 0; regno < 32; regno++)
     supply_register (regno + tdep->ppc_fp0_regnum, (char *) (vals + regno));
 }
@@ -1039,7 +1043,7 @@ special_register_p (int regno)
       || regno == tdep->ppc_lr_regnum
       || regno == tdep->ppc_ctr_regnum
       || regno == tdep->ppc_xer_regnum
-      || regno == tdep->ppc_fpscr_regnum
+      || (tdep->ppc_fpscr_regnum >= 0 && regno == tdep->ppc_fpscr_regnum)
       || (tdep->ppc_mq_regnum >= 0 && regno == tdep->ppc_mq_regnum);
 }
 
@@ -1060,7 +1064,8 @@ supply_sprs64 (uint64_t iar, uint64_t msr, uint32_t cr,
   supply_register (tdep->ppc_lr_regnum, (char *) &lr);
   supply_register (tdep->ppc_ctr_regnum, (char *) &ctr);
   supply_register (tdep->ppc_xer_regnum, (char *) &xer);
-  supply_register (tdep->ppc_fpscr_regnum, (char *) &fpscr);
+  if (tdep->ppc_fpscr_regnum >= 0)
+    supply_register (tdep->ppc_fpscr_regnum, (char *) &fpscr);
 }
 
 /* Record that the special registers contain the specified 32-bit
@@ -1079,7 +1084,8 @@ supply_sprs32 (uint32_t iar, uint32_t msr, uint32_t cr,
   supply_register (tdep->ppc_lr_regnum, (char *) &lr);
   supply_register (tdep->ppc_ctr_regnum, (char *) &ctr);
   supply_register (tdep->ppc_xer_regnum, (char *) &xer);
-  supply_register (tdep->ppc_fpscr_regnum, (char *) &fpscr);
+  if (tdep->ppc_fpscr_regnum >= 0)
+    supply_register (tdep->ppc_fpscr_regnum, (char *) &fpscr);
 }
 
 /* Fetch all registers from pthread PDTID, which doesn't have a kernel
@@ -1113,7 +1119,8 @@ fetch_regs_user_thread (pthdb_pthread_t pdtid)
 
   /* Floating-point registers.  */
 
-  supply_fprs (ctx.fpr);
+  if (ppc_floating_point_p (current_gdbarch))
+    supply_fprs (ctx.fpr);
 
   /* Special registers.  */
 
@@ -1179,9 +1186,10 @@ fetch_regs_kernel_thread (int regno, pthdb_tid_t tid)
 
   /* Floating-point registers.  */
 
-  if (regno == -1
-      || (regno >= tdep->ppc_fp0_regnum
-          && regno < tdep->ppc_fp0_regnum + ppc_num_fprs))
+  if (ppc_floating_point_unit_p (current_gdbarch)
+      && (regno == -1
+          || (regno >= tdep->ppc_fp0_regnum
+              && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)))
     {
       if (!ptrace32 (PTT_READ_FPRS, tid, (int *) fprs, 0, NULL))
        memset (fprs, 0, sizeof (fprs));
@@ -1271,6 +1279,10 @@ fill_fprs (double *vals)
   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
   int regno;
 
+  /* This function should never be called on architectures without
+     floating-point registers.  */
+  gdb_assert (ppc_floating_point_p (current_gdbarch));
+
   for (regno = tdep->ppc_fp0_regnum;
        regno < tdep->ppc_fp0_regnum + ppc_num_fprs;
        regno++)
@@ -1307,7 +1319,8 @@ fill_sprs64 (uint64_t *iar, uint64_t *msr, uint32_t *cr,
     regcache_collect (tdep->ppc_ctr_regnum, ctr);
   if (register_cached (tdep->ppc_xer_regnum))
     regcache_collect (tdep->ppc_xer_regnum, xer);
-  if (register_cached (tdep->ppc_fpscr_regnum))
+  if (tdep->ppc_fpscr_regnum >= 0
+      && register_cached (tdep->ppc_fpscr_regnum))
     regcache_collect (tdep->ppc_fpscr_regnum, fpscr);
 }
 
@@ -1342,7 +1355,8 @@ fill_sprs32 (unsigned long *iar, unsigned long *msr, unsigned long *cr,
     regcache_collect (tdep->ppc_ctr_regnum, ctr);
   if (register_cached (tdep->ppc_xer_regnum))
     regcache_collect (tdep->ppc_xer_regnum, xer);
-  if (register_cached (tdep->ppc_fpscr_regnum))
+  if (tdep->ppc_fpscr_regnum >= 0
+      && register_cached (tdep->ppc_fpscr_regnum))
     regcache_collect (tdep->ppc_fpscr_regnum, fpscr);
 }
 
@@ -1390,7 +1404,8 @@ store_regs_user_thread (pthdb_pthread_t pdtid)
       }
 
   /* Collect floating-point register values from the regcache.  */
-  fill_fprs (ctx.fpr);
+  if (ppc_floating_point_p (current_gdbarch))
+    fill_fprs (ctx.fpr);
 
   /* Special registers (always kept in ctx as 64 bits).  */
   if (arch64)
@@ -1480,9 +1495,10 @@ store_regs_kernel_thread (int regno, pthdb_tid_t tid)
 
   /* Floating-point registers.  */
 
-  if (regno == -1
-      || (regno >= tdep->ppc_fp0_regnum
-          && regno < tdep->ppc_fp0_regnum + ppc_num_fprs))
+  if (ppc_floating_point_unit_p (current_gdbarch)
+      && (regno == -1
+          || (regno >= tdep->ppc_fp0_regnum
+              && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)))
     {
       /* Pre-fetch: some regs may not be in the cache.  */
       ptrace32 (PTT_READ_FPRS, tid, (int *) fprs, 0, NULL);

diff --git a/gdb/ppc-bdm.c b/gdb/ppc-bdm.c
index 59fac1f..cf37b2e 100644 (file)
--- a/gdb/ppc-bdm.c
+++ b/gdb/ppc-bdm.c
@@ -37,6 +37,7 @@
 #include "ocd.h"
 #include "ppc-tdep.h"
 #include "regcache.h"
+#include "gdb_assert.h"
 
 static void bdm_ppc_open (char *name, int from_tty);
 
@@ -193,6 +194,12 @@ bdm_ppc_fetch_registers (int regno)
       return;                  /* Unsupported register */
     }
 
+  /* FIXME: jimb/2004-05-04: I'm not sure how to adapt this code to
+     processors that lack floating point registers, and I don't have
+     have the equipment to test it.  So we'll leave that case for the
+     next person who encounters it.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
 #if 1
   /* Can't ask for floating point regs on ppc 8xx, also need to
      avoid asking for the mq register. */
@@ -287,6 +294,12 @@ bdm_ppc_store_registers (int regno)
   if (first_bdm_regno == -1)
     return;                    /* Unsupported register */
 
+  /* FIXME: jimb/2004-05-04: I'm not sure how to adapt this code to
+     processors that lack floating point registers, and I don't have
+     have the equipment to test it.  So we'll leave that case for the
+     next person who encounters it.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   for (i = first_regno; i <= last_regno; i++)
     {
       int bdm_regno;

diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
index 6d64665..460d48a 100644 (file)
--- a/gdb/ppc-linux-nat.c
+++ b/gdb/ppc-linux-nat.c
@@ -26,6 +26,7 @@
 #include "inferior.h"
 #include "gdbcore.h"
 #include "regcache.h"
+#include "gdb_assert.h"
 
 #include <sys/types.h>
 #include <sys/param.h>
@@ -139,7 +140,8 @@ ppc_register_u_addr (int regno)
   /* Floating point regs: eight bytes each in both 32- and 64-bit
      ptrace interfaces.  Thus, two slots each in 32-bit interface, one
      slot each in 64-bit interface.  */
-  if (regno >= tdep->ppc_fp0_regnum
+  if (tdep->ppc_fp0_regnum >= 0
+      && regno >= tdep->ppc_fp0_regnum
       && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
     u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
 
@@ -160,7 +162,8 @@ ppc_register_u_addr (int regno)
 #endif
   if (regno == tdep->ppc_ps_regnum)
     u_addr = PT_MSR * wordsize;
-  if (regno == tdep->ppc_fpscr_regnum)
+  if (tdep->ppc_fpscr_regnum >= 0
+      && regno == tdep->ppc_fpscr_regnum)
     u_addr = PT_FPSCR * wordsize;
 
   return u_addr;
@@ -234,6 +237,11 @@ fetch_register (int tid, int regno)
       return;
     }
 
+  /* If the current architecture has no floating-point registers, we
+     should never reach this point: ppc_register_u_addr should have
+     returned -1, and we should have caught that above.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   /* Read the raw register using PTRACE_XFER_TYPE sized chunks.  On a
      32-bit platform, 64-bit floating-point registers will require two
      transfers.  */
@@ -412,6 +420,11 @@ store_register (int tid, int regno)
   if (regaddr == -1)
     return;
 
+  /* If the current architecture has no floating-point registers, we
+     should never reach this point: ppc_register_u_addr should have
+     returned -1, and we should have caught that above.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   /* First collect the register value from the regcache.  Be careful
      to to convert the regcache's wordsize into ptrace's wordsize.  */
   memset (buf, 0, sizeof buf);
@@ -436,7 +449,7 @@ store_register (int tid, int regno)
       regaddr += sizeof (PTRACE_XFER_TYPE);
 
       if (errno == EIO 
-          && regno == gdbarch_tdep (current_gdbarch)->ppc_fpscr_regnum)
+          && regno == tdep->ppc_fpscr_regnum)
        {
          /* Some older kernel versions don't allow fpscr to be written.  */
          continue;
@@ -620,11 +633,14 @@ fill_fpregset (gdb_fpregset_t *fpregsetp, int regno)
   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 
   bfd_byte *fpp = (void *) fpregsetp;
   
-  for (regi = 0; regi < 32; regi++)
+  if (ppc_floating_point_unit_p (current_gdbarch))
     {
-      if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi))
-       regcache_collect (tdep->ppc_fp0_regnum + regi, fpp + 8 * regi);
+      for (regi = 0; regi < ppc_num_fprs; regi++)
+        {
+          if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi))
+            regcache_collect (tdep->ppc_fp0_regnum + regi, fpp + 8 * regi);
+        }
+      if (regno == -1 || regno == tdep->ppc_fpscr_regnum)
+        right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32));
     }
-  if ((regno == -1) || regno == tdep->ppc_fpscr_regnum)
-    right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32));
 }

diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c
index 94c67f1..49f4ad6 100644 (file)
--- a/gdb/ppc-linux-tdep.c
+++ b/gdb/ppc-linux-tdep.c
@@ -944,12 +944,16 @@ ppc_linux_sigtramp_cache (struct frame_info *next_frame, void **this_cache)
   cache->saved_regs[tdep->ppc_cr_regnum].addr = gpregs + 38 * tdep->wordsize;
 
   /* Floating point registers.  */
-  for (i = 0; i < 32; i++)
+  if (ppc_floating_point_unit_p (gdbarch))
     {
-      int regnum = i + tdep->ppc_fp0_regnum;
-      cache->saved_regs[regnum].addr = fpregs + i * tdep->wordsize;
+      for (i = 0; i < ppc_num_fprs; i++)
+        {
+          int regnum = i + tdep->ppc_fp0_regnum;
+          cache->saved_regs[regnum].addr = fpregs + i * tdep->wordsize;
+        }
+      cache->saved_regs[tdep->ppc_fpscr_regnum].addr
+        = fpregs + 32 * tdep->wordsize;
     }
-  cache->saved_regs[tdep->ppc_fpscr_regnum].addr = fpregs + 32 * tdep->wordsize;
 
   return cache;
 }
@@ -1018,15 +1022,18 @@ ppc_linux_supply_fpregset (const struct regset *regset,
   struct gdbarch_tdep *regcache_tdep = gdbarch_tdep (regcache_arch);
   const bfd_byte *buf = fpset;
 
-  for (regi = 0; regi < 32; regi++)
+  if (! ppc_floating_point_unit_p (regcache_arch))
+    return;
+
+  for (regi = 0; regi < ppc_num_fprs; regi++)
     regcache_raw_supply (regcache, 
                          regcache_tdep->ppc_fp0_regnum + regi,
                          buf + 8 * regi);
 
-  /* The FPSCR is stored in the low order word of the last doubleword in the
-     fpregset.  */
+  /* The FPSCR is stored in the low order word of the last
+     doubleword in the fpregset.  */
   regcache_raw_supply (regcache, regcache_tdep->ppc_fpscr_regnum,
-                      buf + 8 * 32 + 4);
+                       buf + 8 * 32 + 4);
 }
 
 static struct regset ppc_linux_fpregset = { NULL, ppc_linux_supply_fpregset };

diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index 9bfb68e..a47fdfc 100644 (file)
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -74,8 +74,8 @@ enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarc
 /* From rs6000-tdep.c... */
 int altivec_register_p (int regno);
 
-/* Return non-zero when the architecture has an FPU (or at least when
-   the ABI is using the FPU).  */
+/* Return non-zero if the architecture described by GDBARCH has
+   floating-point registers (f0 --- f31 and fpscr).  */
 int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
 
 /* Register set description.  */
@@ -150,9 +150,13 @@ struct gdbarch_tdep
     int ppc_lr_regnum;         /* Link register */
     int ppc_ctr_regnum;                /* Count register */
     int ppc_xer_regnum;                /* Integer exception register */
+
+    /* On PPC and RS6000 variants that have no floating-point
+       registers, the next two members will be -1.  */
     int ppc_fp0_regnum;         /* floating-point register 0 */
     int ppc_fpscr_regnum;      /* Floating point status and condition
                                   register */
+
     int ppc_mq_regnum;         /* Multiply/Divide extension register */
     int ppc_vr0_regnum;                /* First AltiVec register */
     int ppc_vrsave_regnum;     /* Last AltiVec register */

diff --git a/gdb/ppcnbsd-nat.c b/gdb/ppcnbsd-nat.c
index 9b7a550..453b95d 100644 (file)
--- a/gdb/ppcnbsd-nat.c
+++ b/gdb/ppcnbsd-nat.c
@@ -25,6 +25,7 @@
 
 #include "defs.h"
 #include "inferior.h"
+#include "gdb_assert.h"
 
 #include "ppc-tdep.h"
 #include "ppcnbsd-tdep.h"
@@ -49,6 +50,14 @@ getfpregs_supplies (int regno)
 {
   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 
+  /* FIXME: jimb/2004-05-05: Some PPC variants don't have
+     floating-point registers.  For such variants,
+     tdep->ppc_fp0_regnum and tdep->ppc_fpscr_regnum will be -1.  I
+     don't think NetBSD runs on any of those chips, but we can at
+     least make sure that if someone tries it, they'll get a proper
+     notification.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   return ((regno >= tdep->ppc_fp0_regnum
            && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
          || regno == tdep->ppc_fpscr_regnum);

diff --git a/gdb/ppcnbsd-tdep.c b/gdb/ppcnbsd-tdep.c
index 891b74f..c1d4146 100644 (file)
--- a/gdb/ppcnbsd-tdep.c
+++ b/gdb/ppcnbsd-tdep.c
@@ -111,6 +111,14 @@ ppcnbsd_supply_fpreg (char *fpregs, int regno)
   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
   int i;
 
+  /* FIXME: jimb/2004-05-05: Some PPC variants don't have
+     floating-point registers.  For such variants,
+     tdep->ppc_fp0_regnum and tdep->ppc_fpscr_regnum will be -1.  I
+     don't think NetBSD runs on any of those chips, but we can at
+     least make sure that if someone tries it, they'll get a proper
+     notification.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   for (i = 0; i < ppc_num_fprs; i++)
     {
       if (regno == tdep->ppc_fp0_regnum + i || regno == -1)
@@ -128,6 +136,14 @@ ppcnbsd_fill_fpreg (char *fpregs, int regno)
   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
   int i;
 
+  /* FIXME: jimb/2004-05-05: Some PPC variants don't have
+     floating-point registers.  For such variants,
+     tdep->ppc_fp0_regnum and tdep->ppc_fpscr_regnum will be -1.  I
+     don't think NetBSD runs on any of those chips, but we can at
+     least make sure that if someone tries it, they'll get a proper
+     notification.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   for (i = 0; i < ppc_num_fprs; i++)
     {
       if (regno == tdep->ppc_fp0_regnum + i || regno == -1)

diff --git a/gdb/ppcobsd-tdep.c b/gdb/ppcobsd-tdep.c
index 90381e4..641f372 100644 (file)
--- a/gdb/ppcobsd-tdep.c
+++ b/gdb/ppcobsd-tdep.c
@@ -24,6 +24,7 @@
 #include "osabi.h"
 #include "regcache.h"
 #include "regset.h"
+#include "gdb_assert.h"
 
 #include "gdb_string.h"
 
@@ -46,6 +47,14 @@ ppcobsd_supply_gregset (const struct regset *regset,
                        struct regcache *regcache, int regnum,
                        const void *gregs, size_t len)
 {
+  /* FIXME: jimb/2004-05-05: Some PPC variants don't have
+     floating-point registers.  For such variants,
+     tdep->ppc_fp0_regnum and tdep->ppc_fpscr_regnum will be -1.  I
+     don't think OpenBSD runs on any of those chips, but we can at
+     least make sure that if someone tries it, they'll get a proper
+     notification.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   ppc_supply_gregset (regset, regcache, regnum, gregs, len);
   ppc_supply_fpregset (regset, regcache, regnum, gregs, len);
 }
@@ -60,6 +69,14 @@ ppcobsd_collect_gregset (const struct regset *regset,
                         const struct regcache *regcache, int regnum,
                         void *gregs, size_t len)
 {
+  /* FIXME: jimb/2004-05-05: Some PPC variants don't have
+     floating-point registers.  For such variants,
+     tdep->ppc_fp0_regnum and tdep->ppc_fpscr_regnum will be -1.  I
+     don't think OpenBSD runs on any of those chips, but we can at
+     least make sure that if someone tries it, they'll get a proper
+     notification.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   ppc_collect_gregset (regset, regcache, regnum, gregs, len);
   ppc_collect_fpregset (regset, regcache, regnum, gregs, len);
 }

diff --git a/gdb/rs6000-nat.c b/gdb/rs6000-nat.c
index b80b5a5..5fbf334 100644 (file)
--- a/gdb/rs6000-nat.c
+++ b/gdb/rs6000-nat.c
@@ -159,7 +159,8 @@ regmap (int regno, int *isfloat)
   if (tdep->ppc_gp0_regnum <= regno
       && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
     return regno;
-  else if (tdep->ppc_fp0_regnum <= regno
+  else if (tdep->ppc_fp0_regnum >= 0
+           && tdep->ppc_fp0_regnum <= regno
            && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
     {
       *isfloat = 1;
@@ -177,7 +178,8 @@ regmap (int regno, int *isfloat)
     return CTR;
   else if (regno == tdep->ppc_xer_regnum)
     return XER;
-  else if (regno == tdep->ppc_fpscr_regnum)
+  else if (tdep->ppc_fpscr_regnum >= 0
+           && regno == tdep->ppc_fpscr_regnum)
     return FPSCR;
   else if (tdep->ppc_mq_regnum >= 0 && regno == tdep->ppc_mq_regnum)
     return MQ;
@@ -359,8 +361,9 @@ fetch_inferior_registers (int regno)
        }
 
       /* Read general purpose floating point registers.  */
-      for (regno = 0; regno < ppc_num_fprs; regno++)
-        fetch_register (tdep->ppc_fp0_regnum + regno);
+      if (tdep->ppc_fp0_regnum >= 0)
+        for (regno = 0; regno < ppc_num_fprs; regno++)
+          fetch_register (tdep->ppc_fp0_regnum + regno);
 
       /* Read special registers.  */
       fetch_register (PC_REGNUM);
@@ -369,7 +372,8 @@ fetch_inferior_registers (int regno)
       fetch_register (tdep->ppc_lr_regnum);
       fetch_register (tdep->ppc_ctr_regnum);
       fetch_register (tdep->ppc_xer_regnum);
-      fetch_register (tdep->ppc_fpscr_regnum);
+      if (tdep->ppc_fpscr_regnum >= 0)
+        fetch_register (tdep->ppc_fpscr_regnum);
       if (tdep->ppc_mq_regnum >= 0)
        fetch_register (tdep->ppc_mq_regnum);
     }
@@ -398,8 +402,9 @@ store_inferior_registers (int regno)
        }
 
       /* Write floating point registers.  */
-      for (regno = 0; regno < ppc_num_fprs; regno++)
-        store_register (tdep->ppc_fp0_regnum + regno);
+      if (tdep->ppc_fp0_regnum >= 0)
+        for (regno = 0; regno < ppc_num_fprs; regno++)
+          store_register (tdep->ppc_fp0_regnum + regno);
 
       /* Write special registers.  */
       store_register (PC_REGNUM);
@@ -408,7 +413,8 @@ store_inferior_registers (int regno)
       store_register (tdep->ppc_lr_regnum);
       store_register (tdep->ppc_ctr_regnum);
       store_register (tdep->ppc_xer_regnum);
-      store_register (tdep->ppc_fpscr_regnum);
+      if (tdep->ppc_fpscr_regnum >= 0)
+        store_register (tdep->ppc_fpscr_regnum);
       if (tdep->ppc_mq_regnum >= 0)
        store_register (tdep->ppc_mq_regnum);
     }
@@ -583,9 +589,10 @@ fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
       for (regi = 0; regi < 32; regi++)
         supply_register (regi, (char *) &regs->r64.gpr[regi]);
 
-      for (regi = 0; regi < 32; regi++)
-       supply_register (tdep->ppc_fp0_regnum + regi,
-                         (char *) &regs->r64.fpr[regi]);
+      if (tdep->ppc_fp0_regnum >= 0)
+        for (regi = 0; regi < 32; regi++)
+          supply_register (tdep->ppc_fp0_regnum + regi,
+                           (char *) &regs->r64.fpr[regi]);
 
       supply_register (PC_REGNUM, (char *) &regs->r64.iar);
       supply_register (tdep->ppc_ps_regnum, (char *) &regs->r64.msr);
@@ -593,16 +600,18 @@ fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
       supply_register (tdep->ppc_lr_regnum, (char *) &regs->r64.lr);
       supply_register (tdep->ppc_ctr_regnum, (char *) &regs->r64.ctr);
       supply_register (tdep->ppc_xer_regnum, (char *) &regs->r64.xer);
-      supply_register (tdep->ppc_fpscr_regnum, (char *) &regs->r64.fpscr);
+      if (tdep->ppc_fpscr_regnum >= 0)
+        supply_register (tdep->ppc_fpscr_regnum, (char *) &regs->r64.fpscr);
     }
   else
     {
       for (regi = 0; regi < 32; regi++)
         supply_register (regi, (char *) &regs->r32.gpr[regi]);
 
-      for (regi = 0; regi < 32; regi++)
-       supply_register (tdep->ppc_fp0_regnum + regi,
-                         (char *) &regs->r32.fpr[regi]);
+      if (tdep->ppc_fp0_regnum >= 0)
+        for (regi = 0; regi < 32; regi++)
+          supply_register (tdep->ppc_fp0_regnum + regi,
+                           (char *) &regs->r32.fpr[regi]);
 
       supply_register (PC_REGNUM, (char *) &regs->r32.iar);
       supply_register (tdep->ppc_ps_regnum, (char *) &regs->r32.msr);
@@ -610,7 +619,8 @@ fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
       supply_register (tdep->ppc_lr_regnum, (char *) &regs->r32.lr);
       supply_register (tdep->ppc_ctr_regnum, (char *) &regs->r32.ctr);
       supply_register (tdep->ppc_xer_regnum, (char *) &regs->r32.xer);
-      supply_register (tdep->ppc_fpscr_regnum, (char *) &regs->r32.fpscr);
+      if (tdep->ppc_fpscr_regnum >= 0)
+        supply_register (tdep->ppc_fpscr_regnum, (char *) &regs->r32.fpscr);
       if (tdep->ppc_mq_regnum >= 0)
        supply_register (tdep->ppc_mq_regnum, (char *) &regs->r32.mq);
     }

diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 4ce8fa1..5879c2c 100644 (file)
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -140,16 +140,16 @@ altivec_register_p (int regno)
     return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
 }
 
-/* Use the architectures FP registers?  */
+
+/* Return non-zero if the architecture described by GDBARCH has
+   floating-point registers (f0 --- f31 and fpscr).  */
 int
 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
 {
-  const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
-  if (info->arch == bfd_arch_powerpc)
-    return (info->mach != bfd_mach_ppc_e500);
-  if (info->arch == bfd_arch_rs6000)
-    return 1;
-  return 0;
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+  return (tdep->ppc_fp0_regnum >= 0
+          && tdep->ppc_fpscr_regnum >= 0);
 }
 \f
 
@@ -226,6 +226,8 @@ ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
   size_t offset;
   int i;
 
+  gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
   offset = offsets->f0_offset;
   for (i = tdep->ppc_fp0_regnum;
        i < tdep->ppc_fp0_regnum + ppc_num_fprs;
@@ -301,6 +303,8 @@ ppc_collect_fpregset (const struct regset *regset,
   size_t offset;
   int i;
 
+  gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
   offset = offsets->f0_offset;
   for (i = tdep->ppc_fp0_regnum;
        i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
@@ -1190,6 +1194,11 @@ rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
 
   CORE_ADDR saved_sp;
 
+  /* The calling convention this function implements assumes the
+     processor has floating-point registers.  We shouldn't be using it
+     on PPC variants that lack them.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   /* The first eight words of ther arguments are passed in registers.
      Copy them appropriately.  */
   ii = 0;
@@ -1416,6 +1425,11 @@ rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
   int offset = 0;
   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 
+  /* The calling convention this function implements assumes the
+     processor has floating-point registers.  We shouldn't be using it
+     on PPC variants that lack them.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
     {
 
@@ -1727,6 +1741,9 @@ rs6000_dwarf2_stab_reg_to_regnum (int num)
   if (0 <= num && num <= 31)
     return tdep->ppc_gp0_regnum + num;
   else if (32 <= num && num <= 63)
+    /* FIXME: jimb/2004-05-05: What should we do when the debug info
+       specifies registers the architecture doesn't have?  Our
+       callers don't check the value we return.  */
     return tdep->ppc_fp0_regnum + (num - 32);
   else if (1200 <= num && num < 1200 + 32)
     return tdep->ppc_ev0_regnum + (num - 1200);
@@ -1765,6 +1782,11 @@ rs6000_store_return_value (struct type *type, char *valbuf)
 {
   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 
+  /* The calling convention this function implements assumes the
+     processor has floating-point registers.  We shouldn't be using it
+     on PPC variants that lack them.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
   if (TYPE_CODE (type) == TYPE_CODE_FLT)
 
     /* Floating point values are returned starting from FPR1 and up.
@@ -2445,11 +2467,17 @@ rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
     {
       int i;
       CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
-      for (i = fdata.saved_fpr; i < 32; i++)
-       {
-         cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
-         fpr_addr += 8;
-       }
+
+      /* If skip_prologue says floating-point registers were saved,
+         but the current architecture has no floating-point registers,
+         then that's strange.  But we have no indices to even record
+         the addresses under, so we just ignore it.  */
+      if (ppc_floating_point_unit_p (gdbarch))
+        for (i = fdata.saved_fpr; i < 32; i++)
+          {
+            cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
+            fpr_addr += 8;
+          }
     }
 
   /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
@@ -2763,6 +2791,8 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
         tdep->ppc_xer_regnum = 5;
        tdep->ppc_ev0_regnum = 7;
        tdep->ppc_ev31_regnum = 38;
+        tdep->ppc_fp0_regnum = -1;
+        tdep->ppc_fpscr_regnum = -1;
         set_gdbarch_pc_regnum (gdbarch, 0);
         set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
         set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);