arm64: dts: imx8mq: properly describe IRQ hierarchy

The GPCv2 sits between most of the peripherals and the GIC and
functions as a wakeup controller for the CPU cores.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 892063a..603b2ec 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -11,8 +11,7 @@
 #include "imx8mq-pinfunc.h"
 
 / {
-       /* This should really be the GPC, but we need a driver for this first */
-       interrupt-parent = <&gic>;
+       interrupt-parent = <&gpc>;
 
        #address-cells = <2>;
        #size-cells = <2>;
@@ -257,6 +256,9 @@
                        gpc: gpc@303a0000 {
                                compatible = "fsl,imx8mq-gpc";
                                reg = <0x303a0000 0x10000>;
+                               interrupt-parent = <&gic>;
+                               interrupt-controller;
+                               #interrupt-cells = <3>;
 
                                pgc {
                                        #address-cells = <1>;