using namespace llvm;
using namespace LegalizeActions;
-AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
+AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST,
+ const GCNTargetMachine &TM) {
using namespace TargetOpcode;
const LLT S1= LLT::scalar(1);
namespace llvm {
+class GCNTargetMachine;
class LLVMContext;
+class SISubtarget;
/// This class provides the information for the target register banks.
class AMDGPULegalizerInfo : public LegalizerInfo {
public:
- AMDGPULegalizerInfo();
+ AMDGPULegalizerInfo(const SISubtarget &ST,
+ const GCNTargetMachine &TM);
};
} // End llvm namespace.
#endif
TLInfo(TM, *this) {}
SISubtarget::SISubtarget(const Triple &TT, StringRef GPU, StringRef FS,
- const TargetMachine &TM)
+ const GCNTargetMachine &TM)
: AMDGPUSubtarget(TT, GPU, FS, TM), InstrInfo(*this),
FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),
TLInfo(TM, *this) {
CallLoweringInfo.reset(new AMDGPUCallLowering(*getTargetLowering()));
- Legalizer.reset(new AMDGPULegalizerInfo());
+ Legalizer.reset(new AMDGPULegalizerInfo(*this, TM));
RegBankInfo.reset(new AMDGPURegisterBankInfo(*getRegisterInfo()));
InstSelector.reset(new AMDGPUInstructionSelector(
public:
SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
- const TargetMachine &TM);
+ const GCNTargetMachine &TM);
const SIInstrInfo *getInstrInfo() const override {
return &InstrInfo;