drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency

[ Upstream commit 4d0a72b66065dd7e274bad6aa450196d42fd8f84 ]

Only send non-0 clocks to DC for validation.  This mirrors
what the windows driver does.

Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 1115761982a78fe2f60efee236fa047d1a10811a..627a42e8fd31840c20c11afd577d821c085fa763 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1026,12 +1026,15 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
 
        clocks->num_levels = 0;
        for (i = 0; i < pclk_vol_table->count; i++) {
-               clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
-               clocks->data[i].latency_in_us = latency_required ?
-                                               smu10_get_mem_latency(hwmgr,
-                                               pclk_vol_table->entries[i].clk) :
-                                               0;
-               clocks->num_levels++;
+               if (pclk_vol_table->entries[i].clk) {
+                       clocks->data[clocks->num_levels].clocks_in_khz =
+                               pclk_vol_table->entries[i].clk * 10;
+                       clocks->data[clocks->num_levels].latency_in_us = latency_required ?
+                               smu10_get_mem_latency(hwmgr,
+                                                     pclk_vol_table->entries[i].clk) :
+                               0;
+                       clocks->num_levels++;
+               }
        }
 
        return 0;