drm/amd/powerplay: fix wrong clock adjust sequence

The clocks should be adjusted after display configuration changed.
Otherwise, the socclk and memclk may be forced on an unnecessary higher
level.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
index 0af13c1..323990b 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -265,19 +265,18 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
        if (skip)
                return 0;
 
-       if (!hwmgr->ps)
-               /*
-                * for vega12/vega20 which does not support power state manager
-                * DAL clock limits should also be honoured
-                */
-               phm_apply_clock_adjust_rules(hwmgr);
-
        phm_pre_display_configuration_changed(hwmgr);
 
        phm_display_configuration_changed(hwmgr);
 
        if (hwmgr->ps)
                power_state_management(hwmgr, new_ps);
+       else
+               /*
+                * for vega12/vega20 which does not support power state manager
+                * DAL clock limits should also be honoured
+                */
+               phm_apply_clock_adjust_rules(hwmgr);
 
        phm_notify_smc_display_config_after_ps_adjustment(hwmgr);