The board features a 128MiB NAND chip and recently linux gained support
for the NAND controller on the Zynq SoC. Thus add the corresponding
devicetree nodes.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20210616155437.27378-4-michael@walle.cc
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
pinctrl-0 = <&pinctrl_gpio0_default>;
};
+&nfc0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
+};
+
&pinctrl0 {
pinctrl_gpio0_default: gpio0-default {
mux {
};
};
+&smcc {
+ status = "okay";
+};
+
&sdhci0 {
status = "okay";
disable-wp;