(define_insn "zero_extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "0,r,m")))]
+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "0,r,q")))]
""
"@
and\t%0,0xffff
(define_insn "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "0,r,m")))]
+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "0,r,q")))]
""
"@
and\t%0,0xff
(define_insn "zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
+ (match_operand:SI 1 "nonimmediate_operand" "r,q")))]
""
"@
* return bpf_has_alu32 ? \"mov32\t%0,%1\" : \"mov\t%0,%1\;and\t%0,0xffffffff\";
}")
(define_insn "*mov<MM:mode>"
- [(set (match_operand:MM 0 "nonimmediate_operand" "=r, r,r,m,m")
- (match_operand:MM 1 "mov_src_operand" " m,rI,B,r,I"))]
+ [(set (match_operand:MM 0 "nonimmediate_operand" "=r, r,r,q,q")
+ (match_operand:MM 1 "mov_src_operand" " q,rI,B,r,I"))]
""
"@
ldx<mop>\t%0,%1
(define_constraint "S"
"A constant call address."
(match_code "const,symbol_ref,label_ref,const_int"))
+
+;;
+;; Memory constraints.
+;;
+
+; Just like 'm' but disallows const_int.
+; Used for ldx[b,h,w,dw] and stx[b,h,w,dw] instructions.
+(define_memory_constraint "q"
+ "Memory reference which is not a constant integer."
+ (and (match_code "mem")
+ (match_test "GET_CODE(XEXP(op, 0)) != CONST_INT")))
--- /dev/null
+/* Verify that we do not generate a malformed ldxdw instruction
+ with a constant instead of register + offset. */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-times "ldxdw\t%r.,\\\[%r.+0\\\]" 1 } } */
+/* { dg-final { scan-assembler-not "ldxdw\t%r.,\[0-9\]+" } } */
+
+unsigned long long test () {
+ return *((unsigned long long *) 0x4000);
+}