According to Bspec, COMPCS0_CCS_AUX_INV register offset
is 042C8h and COMPCS0_AUX_TABLE_BASE_ADDR is defined to 042C0h.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958>
#if GFX_VER == 12
if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) && device->info->has_aux_map) {
uint64_t register_addr =
- current_pipeline == GPGPU ? GENX(CCS_CCS_AUX_INV_num) :
+ current_pipeline == GPGPU ? GENX(COMPCS0_CCS_AUX_INV_num) :
GENX(GFX_CCS_AUX_INV_num);
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
lri.RegisterOffset = register_addr;
anv_address_from_u64(register_addr);
}
}
+#else
+ assert(!device->info->has_aux_map);
#endif
bits &= ~ANV_PIPE_INVALIDATE_BITS;