arm64: dts: meson-sm1: add cpu thermal nodes

Add thermal nodes for the Amlogic SM1 SoCs based on the G12A and G12B
thermal nodes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512093916.19676-3-narmstrong@baylibre.com

diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index d4ec735fb1a5cadeac0488c5b4b0e51289a7c7c4..71317f5aada1d7da57f9f24625fd4122eb004c0f 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -56,6 +56,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                cpu1: cpu@1 {
@@ -64,6 +65,7 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                cpu2: cpu@2 {
@@ -72,6 +74,7 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                cpu3: cpu@3 {
@@ -80,6 +83,7 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                l2: l2-cache0 {
@@ -466,6 +470,26 @@
        compatible = "amlogic,sm1-clkc";
 };
 
+&cpu_thermal {
+       cooling-maps {
+               map0 {
+                       trip = <&cpu_passive>;
+                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+               };
+
+               map1 {
+                       trip = <&cpu_hot>;
+                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+               };
+       };
+};
+
 &ethmac {
        power-domains = <&pwrc PWRC_SM1_ETH_ID>;
 };