ARM: uniphier: fix SSCPLL init code for LD11 SoC
authorDai Okamura <okamura.dai@socionext.com>
Wed, 6 Dec 2017 05:16:32 +0000 (14:16 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Mon, 11 Dec 2017 15:36:11 +0000 (00:36 +0900)
Commit 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC")
missed to write the computed value to the SSCPLLCTRL2 register.

Fixes: 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC")
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm/mach-uniphier/clk/pll-base-ld20.c

index 3aa42f8bfdcd9909e3aae3cc5bf8f31aeba94775..45fdf0a3226c376066b64d5cfb803f00f733305f 100644 (file)
@@ -48,6 +48,7 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
                tmp = readl(base + 4);
                tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
                tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
+               writel(tmp, base + 4);
 
                udelay(50);
        }