RISC-V: add missing single letter extension definitions
authorConor Dooley <conor.dooley@microchip.com>
Thu, 13 Jul 2023 12:11:04 +0000 (13:11 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Tue, 25 Jul 2023 23:26:20 +0000 (16:26 -0700)
To facilitate adding single letter extensions to riscv_isa_ext, add
definitions for the extensions present in base_riscv_exts that do not
already have them.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230713-train-feisty-93de38250f98@wendy
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/hwcap.h

index 2460ac2..a20e4ad 100644 (file)
 #include <uapi/asm/hwcap.h>
 
 #define RISCV_ISA_EXT_a                ('a' - 'a')
+#define RISCV_ISA_EXT_b                ('b' - 'a')
 #define RISCV_ISA_EXT_c                ('c' - 'a')
 #define RISCV_ISA_EXT_d                ('d' - 'a')
 #define RISCV_ISA_EXT_f                ('f' - 'a')
 #define RISCV_ISA_EXT_h                ('h' - 'a')
 #define RISCV_ISA_EXT_i                ('i' - 'a')
+#define RISCV_ISA_EXT_j                ('j' - 'a')
+#define RISCV_ISA_EXT_k                ('k' - 'a')
 #define RISCV_ISA_EXT_m                ('m' - 'a')
+#define RISCV_ISA_EXT_p                ('p' - 'a')
+#define RISCV_ISA_EXT_q                ('q' - 'a')
 #define RISCV_ISA_EXT_s                ('s' - 'a')
 #define RISCV_ISA_EXT_u                ('u' - 'a')
 #define RISCV_ISA_EXT_v                ('v' - 'a')