clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks

On the H6, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.

To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.

This patch adds the post-dividers to the MMC clocks, following the
approach on A64.

Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index d425b47..2193e14 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -408,26 +408,29 @@ static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
 
 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
                                            "pll-periph1-2x" };
-static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_parents, 0x830,
-                                       0, 4,   /* M */
-                                       8, 2,   /* N */
-                                       24, 3,  /* mux */
-                                       BIT(31),/* gate */
-                                       0);
-
-static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_parents, 0x834,
-                                       0, 4,   /* M */
-                                       8, 2,   /* N */
-                                       24, 3,  /* mux */
-                                       BIT(31),/* gate */
-                                       0);
-
-static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_parents, 0x838,
-                                       0, 4,   /* M */
-                                       8, 2,   /* N */
-                                       24, 3,  /* mux */
-                                       BIT(31),/* gate */
-                                       0);
+static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
+                                         0, 4,         /* M */
+                                         8, 2,         /* N */
+                                         24, 3,        /* mux */
+                                         BIT(31),      /* gate */
+                                         2,            /* post-div */
+                                         0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
+                                         0, 4,         /* M */
+                                         8, 2,         /* N */
+                                         24, 3,        /* mux */
+                                         BIT(31),      /* gate */
+                                         2,            /* post-div */
+                                         0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
+                                         0, 4,         /* M */
+                                         8, 2,         /* N */
+                                         24, 3,        /* mux */
+                                         BIT(31),      /* gate */
+                                         2,            /* post-div */
+                                         0);
 
 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);