NVC3C0_QMDV02_02_VAL_SET(qmd, REGISTER_COUNT_V, shader->num_gprs);
NVC3C0_QMDV02_02_VAL_SET(qmd, BARRIER_COUNT, shader->num_barriers);
- uint64_t entry = shader->bo->offset;
- NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_LOWER, entry & 0xffffffff);
- NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_UPPER, entry >> 32);
+ uint64_t addr = nvk_shader_address(shader);
+ NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_LOWER, addr & 0xffffffff);
+ NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_UPPER, addr >> 32);
}
#define NVK_SHADER_H 1
#include "nvk_private.h"
+#include "nvk_device_memory.h"
#include "nir.h"
+#include "nouveau_bo.h"
struct vk_shader_module;
struct nvk_device;
struct nouveau_ws_bo *bo;
};
+static inline uint64_t
+nvk_shader_address(const struct nvk_shader *shader)
+{
+ return shader->bo->offset;
+}
+
const nir_shader_compiler_options *
nvk_physical_device_nir_options(const struct nvk_physical_device *pdevice,
gl_shader_stage stage);