dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP

CMU_CMGP generates USI and ADC clocks for BLK_ALIVE. In particular USI
clocks are needed for HSI2C_3 and HSI2C_4 instances.

Add clock indices and bindings documentation for CMU_CMGP domain.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211121232741.6967-4-semen.protsenko@linaro.org

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
index 5618cfa62f805c13de56b1765d021e77df005d00..80ba60838f2badc08c75edda51540955d0a7bd2d 100644 (file)
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -33,6 +33,7 @@ properties:
     enum:
       - samsung,exynos850-cmu-top
       - samsung,exynos850-cmu-apm
+      - samsung,exynos850-cmu-cmgp
       - samsung,exynos850-cmu-core
       - samsung,exynos850-cmu-dpu
       - samsung,exynos850-cmu-hsi
@@ -87,6 +88,24 @@ allOf:
             - const: oscclk
             - const: dout_clkcmu_apm_bus
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-cmgp
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_CMGP bus clock (from CMU_APM)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: gout_clkcmu_cmgp_bus
+
   - if:
       properties:
         compatible:

diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index df3978b58304c2faef28a14a706ae59543774002..8aa5e82af0d37acc9c60d0b1985f1fcd3227350a 100644 (file)
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -84,6 +84,23 @@
 #define CLK_GOUT_SPEEDY_PCLK           21
 #define APM_NR_CLK                     22
 
+/* CMU_CMGP */
+#define CLK_RCO_CMGP                   1
+#define CLK_MOUT_CMGP_ADC              2
+#define CLK_MOUT_CMGP_USI0             3
+#define CLK_MOUT_CMGP_USI1             4
+#define CLK_DOUT_CMGP_ADC              5
+#define CLK_DOUT_CMGP_USI0             6
+#define CLK_DOUT_CMGP_USI1             7
+#define CLK_GOUT_CMGP_ADC_S0_PCLK      8
+#define CLK_GOUT_CMGP_ADC_S1_PCLK      9
+#define CLK_GOUT_CMGP_GPIO_PCLK                10
+#define CLK_GOUT_CMGP_USI0_IPCLK       11
+#define CLK_GOUT_CMGP_USI0_PCLK                12
+#define CLK_GOUT_CMGP_USI1_IPCLK       13
+#define CLK_GOUT_CMGP_USI1_PCLK                14
+#define CMGP_NR_CLK                    15
+
 /* CMU_HSI */
 #define CLK_MOUT_HSI_BUS_USER          1
 #define CLK_MOUT_HSI_MMC_CARD_USER     2