hdmitx: fix bsod and path dealy under hdcp22

PD#166207: hdmitx: fix bsod and path dealy under hdcp22

1.HDMITX_TOP_HDCP22_BSOD[25] doesn't use bsod
2.HDCP22REG_CTRL[6.7] match path delays
  between hdcp path and non-hdcp path

Change-Id: I295804895f715687f975ab8ecfb7ea348999095a
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
index 904bc67..8cb746b 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -3399,13 +3399,10 @@ static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd,
                break;
        case DDC_HDCP_MUX_INIT:
                if (argv == 2) {
-                       /*hdmitx_set_reg_bits
-                        *      (HDMITX_TOP_HDCP22_BSOD, 1, 25, 1);
-                        */
                        hdmitx_ddc_hw_op(DDC_MUX_DDC);
                        hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, 1, 6, 1);
                        udelay(5);
-                       hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_CTRL, 0x86);
+                       hdmitx_set_reg_bits(HDMITX_DWC_HDCP22REG_CTRL, 3, 1, 2);
                        hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 1, 5, 1);
                        udelay(10);
                        hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 0, 5, 1);