The WM8350 driver was using some custom constants to interpret the direction
of the MCLK signal which had the opposite values to those used as standard
by the ASoC core, causing confusion in machine drivers such as the 1133-EV1
board.
Reported-by: Tommy Zhu <Tommy.Zhu@wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
#define WM8350_MCLK_SEL_PLL_32K 3
#define WM8350_MCLK_SEL_MCLK 5
-#define WM8350_MCLK_DIR_OUT 0
-#define WM8350_MCLK_DIR_IN 1
-
/* clock divider id's */
#define WM8350_ADC_CLKDIV 0
#define WM8350_DAC_CLKDIV 1
}
/* MCLK direction */
- if (dir == WM8350_MCLK_DIR_OUT)
+ if (dir == SND_SOC_CLOCK_OUT)
wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
WM8350_MCLK_DIR);
else