{
if (TARGET_POWERPC)
emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
- else if (TARGET_POWER)
- emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
else
emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
DONE;
(const_int 0)))]
"")
-(define_expand "extendqisi2_power"
- [(parallel [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
- (const_int 24)))
- (clobber (scratch:SI))])
- (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 2)
- (const_int 24)))
- (clobber (scratch:SI))])]
- "TARGET_POWER"
- "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
-
(define_expand "extendqisi2_no_power"
[(set (match_dup 2)
(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
(set (match_operand:SI 0 "gpc_reg_operand" "")
(ashiftrt:SI (match_dup 2)
(const_int 24)))]
- "! TARGET_POWER && ! TARGET_POWERPC"
+ "! TARGET_POWERPC"
"
{ operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_reg_rtx (SImode); }")
{
if (TARGET_POWERPC)
emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
- else if (TARGET_POWER)
- emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
else
emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
DONE;
(const_int 0)))]
"")
-(define_expand "extendqihi2_power"
- [(parallel [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
- (const_int 24)))
- (clobber (scratch:SI))])
- (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 2)
- (const_int 24)))
- (clobber (scratch:SI))])]
- "TARGET_POWER"
- "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
-
(define_expand "extendqihi2_no_power"
[(set (match_dup 2)
(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
(set (match_operand:HI 0 "gpc_reg_operand" "")
(ashiftrt:SI (match_dup 2)
(const_int 24)))]
- "! TARGET_POWER && ! TARGET_POWERPC"
+ "! TARGET_POWERPC"
"
{ operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
}
}")
-;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
-;; instruction and some auxiliary computations. Then we just have a single
-;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
-;; combine.
-
(define_expand "sminsi3"
[(set (match_dup 3)
(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
(minus:SI (match_dup 2) (match_dup 1))))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_dup 2) (match_dup 3)))]
- "TARGET_POWER || TARGET_ISEL"
+ "TARGET_ISEL"
"
{
- if (TARGET_ISEL)
- {
- operands[2] = force_reg (SImode, operands[2]);
- rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
+ operands[2] = force_reg (SImode, operands[2]);
+ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
+ DONE;
}")
-(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" "")))
- (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
- "TARGET_POWER"
- [(set (match_dup 3)
- (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
- "")
-
(define_expand "smaxsi3"
[(set (match_dup 3)
(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
(minus:SI (match_dup 2) (match_dup 1))))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 3) (match_dup 1)))]
- "TARGET_POWER || TARGET_ISEL"
+ "TARGET_ISEL"
"
{
- if (TARGET_ISEL)
- {
- operands[2] = force_reg (SImode, operands[2]);
- rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
- DONE;
- }
- operands[3] = gen_reg_rtx (SImode);
+ operands[2] = force_reg (SImode, operands[2]);
+ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
+ DONE;
}")
-(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" "")))
- (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
- "TARGET_POWER"
- [(set (match_dup 3)
- (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
- "")
-
(define_expand "uminsi3"
[(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_dup 5)))
(minus:SI (match_dup 4) (match_dup 3))))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_dup 2) (match_dup 3)))]
- "TARGET_POWER || TARGET_ISEL"
+ "TARGET_ISEL"
"
{
- if (TARGET_ISEL)
- {
- rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
- DONE;
- }
- operands[3] = gen_reg_rtx (SImode);
- operands[4] = gen_reg_rtx (SImode);
- operands[5] = GEN_INT (-2147483647 - 1);
+ rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
+ DONE;
}")
(define_expand "umaxsi3"
(minus:SI (match_dup 4) (match_dup 3))))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 3) (match_dup 1)))]
- "TARGET_POWER || TARGET_ISEL"
+ "TARGET_ISEL"
"
{
- if (TARGET_ISEL)
- {
- rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
- DONE;
- }
- operands[3] = gen_reg_rtx (SImode);
- operands[4] = gen_reg_rtx (SImode);
- operands[5] = GEN_INT (-2147483647 - 1);
+ rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
+ DONE;
}")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2")
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1)))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_POWER"
- "@
- doz%I2. %3,%1,%2
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1)))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 3)
- (if_then_else:SI (gt (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (if_then_else:SI (gt (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))]
- "TARGET_POWER"
- "@
- doz%I2. %0,%1,%2
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (if_then_else:SI (gt (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (if_then_else:SI (gt (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
;; We don't need abs with condition code because such comparisons should
;; never be done.
(define_expand "abssi2"
emit_insn (gen_abssi2_isel (operands[0], operands[1]));
DONE;
}
- else if (! TARGET_POWER)
+ else
{
emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
DONE;
}
}")
-(define_insn "*abssi2_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_POWER"
- "abs %0,%1")
-
(define_insn_and_split "abs<mode>2_isel"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
(clobber (match_scratch:SI 2 "=&r,&r"))]
- "! TARGET_POWER && ! TARGET_ISEL"
+ "! TARGET_ISEL"
"#"
"&& reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
"")
-(define_insn "*nabs_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
- "TARGET_POWER"
- "nabs %0,%1")
-
(define_insn_and_split "*nabs_nopower"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
(clobber (match_scratch:SI 2 "=&r,&r"))]
- "! TARGET_POWER"
+ ""
"#"
"&& reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
emit_insn (gen_bswapsi2 (dest_low, src_high));
}")
-(define_expand "mulsi3"
- [(use (match_operand:SI 0 "gpc_reg_operand" ""))
- (use (match_operand:SI 1 "gpc_reg_operand" ""))
- (use (match_operand:SI 2 "reg_or_short_operand" ""))]
- ""
- "
-{
- if (TARGET_POWER)
- emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_insn "mulsi3_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,I")))
- (clobber (match_scratch:SI 3 "=q,q"))]
- "TARGET_POWER"
- "@
- {muls|mullw} %0,%1,%2
- {muli|mulli} %0,%1,%2"
- [(set (attr "type")
- (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
- (const_string "imul3")
- (match_operand:SI 2 "short_cint_operand" "")
- (const_string "imul2")]
- (const_string "imul")))])
-
-(define_insn "mulsi3_no_mq"
+(define_insn "mulsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))]
- "! TARGET_POWER"
+ ""
"@
{muls|mullw} %0,%1,%2
{muli|mulli} %0,%1,%2"
(const_string "imul2")]
(const_string "imul")))])
-(define_insn "*mulsi3_mq_internal1"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))
- (clobber (match_scratch:SI 4 "=q,q"))]
- "TARGET_POWER"
- "@
- {muls.|mullw.} %3,%1,%2
- #"
- [(set_attr "type" "imul_compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 3)
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*mulsi3_no_mq_internal1"
+(define_insn "*mulsi3_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
- "! TARGET_POWER"
+ ""
"@
{muls.|mullw.} %3,%1,%2
#"
(match_operand:SI 2 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWER && reload_completed"
+ "reload_completed"
[(set (match_dup 3)
(mult:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(const_int 0)))]
"")
-(define_insn "*mulsi3_mq_internal2"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 "=q,q"))]
- "TARGET_POWER"
- "@
- {muls.|mullw.} %0,%1,%2
- #"
- [(set_attr "type" "imul_compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*mulsi3_no_mq_internal2"
+(define_insn "*mulsi3_internal2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(mult:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER"
+ ""
"@
{muls.|mullw.} %0,%1,%2
#"
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(mult:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(mult:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(match_operand:SI 2 "gpc_reg_operand" "")))
(set (match_operand:SI 3 "register_operand" "")
(mod:SI (match_dup 1) (match_dup 2)))])]
- "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
+ "! TARGET_POWERPC"
"
{
- if (! TARGET_POWER && ! TARGET_POWERPC)
- {
- emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
- emit_insn (gen_divss_call ());
- emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
- emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
- DONE;
- }
+ emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
+ emit_insn (gen_divss_call ());
+ emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
+ emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
+ DONE;
}")
-(define_insn "*divmodsi4_internal"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (set (match_operand:SI 3 "register_operand" "=q")
- (mod:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER"
- "divs %0,%1,%2"
- [(set_attr "type" "idiv")])
-
(define_expand "udiv<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "")
(udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
(match_operand:GPR 2 "gpc_reg_operand" "")))]
- "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
+ ""
"
{
- if (! TARGET_POWER && ! TARGET_POWERPC)
+ if (! TARGET_POWERPC)
{
emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
DONE;
}
- else if (TARGET_POWER)
- {
- emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
}")
-(define_insn "udivsi3_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWERPC && TARGET_POWER"
- "divwu %0,%1,%2"
- [(set_attr "type" "idiv")])
-
-(define_insn "*udivsi3_no_mq"
+(define_insn "*udivsi3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC && ! TARGET_POWER"
+ "TARGET_POWERPC"
"div<wd>u %0,%1,%2"
[(set (attr "type")
(cond [(match_operand:SI 0 "" "")
;; For powers of two we can do srai/aze for divide and then adjust for
-;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
-;; used; for PowerPC, force operands into register and do a normal divide;
-;; for AIX common-mode, use quoss call on register operands.
+;; modulus. If it isn't a power of two, force operands into register and do
+;; a normal divide; for AIX common-mode, use quoss call on register operands.
(define_expand "div<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "")
(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
else if (TARGET_POWERPC)
{
operands[2] = force_reg (<MODE>mode, operands[2]);
- if (TARGET_POWER)
- {
- emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
}
- else if (TARGET_POWER)
- FAIL;
else
{
emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
}
}")
-(define_insn "divsi3_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWERPC && TARGET_POWER"
- "divw %0,%1,%2"
- [(set_attr "type" "idiv")])
-
(define_insn "*div<mode>3_no_mq"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC && ! TARGET_POWER"
+ "TARGET_POWERPC"
"div<wd> %0,%1,%2"
[(set (attr "type")
(cond [(match_operand:SI 0 "" "")
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (udiv:SI
- (plus:DI (ashift:DI
- (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (const_int 32))
- (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
- (match_operand:SI 3 "gpc_reg_operand" "r")))
- (set (match_operand:SI 2 "register_operand" "=*q")
- (umod:SI
- (plus:DI (ashift:DI
- (zero_extend:DI (match_dup 1)) (const_int 32))
- (zero_extend:DI (match_dup 4)))
- (match_dup 3)))]
- "TARGET_POWER"
- "div %0,%1,%3"
- [(set_attr "type" "idiv")])
-
-;; To do unsigned divide we handle the cases of the divisor looking like a
-;; negative number. If it is a constant that is less than 2**31, we don't
-;; have to worry about the branches. So make a few subroutines here.
-;;
-;; First comes the normal case.
-(define_expand "udivmodsi4_normal"
- [(set (match_dup 4) (const_int 0))
- (parallel [(set (match_operand:SI 0 "" "")
- (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
- (const_int 32))
- (zero_extend:DI (match_operand:SI 1 "" "")))
- (match_operand:SI 2 "" "")))
- (set (match_operand:SI 3 "" "")
- (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
- (const_int 32))
- (zero_extend:DI (match_dup 1)))
- (match_dup 2)))])]
- "TARGET_POWER"
- "
-{ operands[4] = gen_reg_rtx (SImode); }")
-
-;; This handles the branches.
-(define_expand "udivmodsi4_tests"
- [(set (match_operand:SI 0 "" "") (const_int 0))
- (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
- (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
- (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
- (label_ref (match_operand:SI 4 "" "")) (pc)))
- (set (match_dup 0) (const_int 1))
- (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
- (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
- (label_ref (match_dup 4)) (pc)))]
- "TARGET_POWER"
- "
-{ operands[5] = gen_reg_rtx (CCUNSmode);
- operands[6] = gen_reg_rtx (CCmode);
-}")
-
(define_expand "udivmodsi4"
[(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
(udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
""
"
{
- rtx label = 0;
-
- if (! TARGET_POWER)
- {
- if (! TARGET_POWERPC)
- {
- emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
- emit_insn (gen_divus_call ());
- emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
- emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
- DONE;
- }
- else
- FAIL;
- }
-
- if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
+ if (! TARGET_POWERPC)
{
- operands[2] = force_reg (SImode, operands[2]);
- label = gen_label_rtx ();
- emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
- operands[3], label));
+ emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
+ emit_insn (gen_divus_call ());
+ emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
+ emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
+ DONE;
}
else
- operands[2] = force_reg (SImode, operands[2]);
-
- emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
- operands[3]));
- if (label)
- emit_label (label);
-
- DONE;
+ FAIL;
}")
;; AIX architecture-independent common-mode multiply (DImode),
(sign_extend:DI (reg:SI 4)))
(const_int 32))))
(clobber (reg:SI LR_REGNO))]
- "! TARGET_POWER && ! TARGET_POWERPC"
+ "! TARGET_POWERPC"
"bla __mulh"
[(set_attr "type" "imul")])
(sign_extend:DI (reg:SI 4))))
(clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))]
- "! TARGET_POWER && ! TARGET_POWERPC"
+ "! TARGET_POWERPC"
"bla __mull"
[(set_attr "type" "imul")])
(mod:SI (reg:SI 3) (reg:SI 4)))
(clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))]
- "! TARGET_POWER && ! TARGET_POWERPC"
+ "! TARGET_POWERPC"
"bla __divss"
[(set_attr "type" "idiv")])
(clobber (reg:SI 0))
(clobber (match_scratch:CC 0 "=x"))
(clobber (reg:CC CR1_REGNO))]
- "! TARGET_POWER && ! TARGET_POWERPC"
+ "! TARGET_POWERPC"
"bla __divus"
[(set_attr "type" "idiv")])
[(set (reg:SI 3)
(div:SI (reg:SI 3) (reg:SI 4)))
(clobber (reg:SI LR_REGNO))]
- "! TARGET_POWER && ! TARGET_POWERPC"
+ "! TARGET_POWERPC"
"bla __quoss"
[(set_attr "type" "idiv")])
(clobber (reg:SI 0))
(clobber (match_scratch:CC 0 "=x"))
(clobber (reg:CC CR1_REGNO))]
- "! TARGET_POWER && ! TARGET_POWERPC"
+ "! TARGET_POWERPC"
"bla __quous"
[(set_attr "type" "idiv")])
\f
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-
-;; maskir insn. We need four forms because things might be in arbitrary
-;; orders. Don't define forms that only set CR fields because these
-;; would modify an input register.
-
-(define_insn "*maskir_internal1"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
- (match_operand:SI 1 "gpc_reg_operand" "0"))
- (and:SI (match_dup 2)
- (match_operand:SI 3 "gpc_reg_operand" "r"))))]
- "TARGET_POWER"
- "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
- (match_operand:SI 1 "gpc_reg_operand" "0"))
- (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
- (match_dup 2))))]
- "TARGET_POWER"
- "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (match_operand:SI 3 "gpc_reg_operand" "r"))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "0"))))]
- "TARGET_POWER"
- "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal4"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "0"))))]
- "TARGET_POWER"
- "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal5"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (match_operand:SI 1 "gpc_reg_operand" "0,0"))
- (and:SI (match_dup 2)
- (match_operand:SI 3 "gpc_reg_operand" "r,r")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 2) (match_dup 3))))]
- "TARGET_POWER"
- "@
- maskir. %0,%3,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (and:SI (match_dup 2)
- (match_operand:SI 3 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 2) (match_dup 3))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 2) (match_dup 3))))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*maskir_internal6"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (match_operand:SI 1 "gpc_reg_operand" "0,0"))
- (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
- (match_dup 2)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 3) (match_dup 2))))]
- "TARGET_POWER"
- "@
- maskir. %0,%3,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
- (match_dup 2)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 3) (match_dup 2))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 3) (match_dup 2))))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*maskir_internal7"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "0,0")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (and:SI (match_dup 2) (match_dup 3))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
- "TARGET_POWER"
- "@
- maskir. %0,%3,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (and:SI (match_dup 2) (match_dup 3))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (ior:SI (and:SI (match_dup 2) (match_dup 3))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*maskir_internal8"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "0,0")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (and:SI (match_dup 3) (match_dup 2))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
- "TARGET_POWER"
- "@
- maskir. %0,%3,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (and:SI (match_dup 3) (match_dup 2))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (ior:SI (and:SI (match_dup 3) (match_dup 2))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
\f
;; Rotate and shift insns, in all their variants. These support shifts,
;; field inserts and extracts, and various combinations thereof.
(const_int 0)))]
"")
-;; Note that we use "sle." instead of "sl." so that we can set
-;; SHIFT_COUNT_TRUNCATED.
-
-(define_expand "ashlsi3"
- [(use (match_operand:SI 0 "gpc_reg_operand" ""))
- (use (match_operand:SI 1 "gpc_reg_operand" ""))
- (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
- ""
- "
-{
- if (TARGET_POWER)
- emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_insn "ashlsi3_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
- (clobber (match_scratch:SI 3 "=q,X"))]
- "TARGET_POWER"
- "@
- sle %0,%1,%2
- {sli|slwi} %0,%1,%h2")
-
-(define_insn "ashlsi3_no_power"
+(define_insn "ashlsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
- "! TARGET_POWER"
+ ""
"@
{sl|slw} %0,%1,%2
{sli|slwi} %0,%1,%h2"
{sli|slwi} %0,%1,%h2"
[(set_attr "type" "var_shift_rotate,shift")])
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))
- (clobber (match_scratch:SI 4 "=q,X,q,X"))]
- "TARGET_POWER"
- "@
- sle. %3,%1,%2
- {sli.|slwi.} %3,%1,%h2
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 3)
- (ashift:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r"))]
- "! TARGET_POWER && TARGET_32BIT"
+ "TARGET_32BIT"
"@
{sl.|slw.} %3,%1,%2
{sli.|slwi.} %3,%1,%h2
(match_operand:SI 2 "reg_or_cint_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWER && TARGET_32BIT && reload_completed"
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 3)
(ashift:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (ashift:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 "=q,X,q,X"))]
- "TARGET_POWER"
- "@
- sle. %0,%1,%2
- {sli.|slwi.} %0,%1,%h2
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashift:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(ashift:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && TARGET_32BIT"
+ "TARGET_32BIT"
"@
{sl.|slw.} %0,%1,%2
{sli.|slwi.} %0,%1,%h2
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(ashift:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && TARGET_32BIT && reload_completed"
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(ashift:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(const_int 0)))]
"")
-;; The AIX assembler mis-handles "sri x,x,0", so write that case as
-;; "sli x,x,0".
-(define_expand "lshrsi3"
- [(use (match_operand:SI 0 "gpc_reg_operand" ""))
- (use (match_operand:SI 1 "gpc_reg_operand" ""))
- (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
- ""
- "
-{
- if (TARGET_POWER)
- emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_insn "lshrsi3_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
- (clobber (match_scratch:SI 3 "=q,X,X"))]
- "TARGET_POWER"
- "@
- sre %0,%1,%2
- mr %0,%1
- {s%A2i|s%A2wi} %0,%1,%h2")
-
-(define_insn "lshrsi3_no_power"
+(define_insn "lshrsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
- "! TARGET_POWER"
+ ""
"@
mr %0,%1
{sr|srw} %0,%1,%2
{sri|srwi} %0,%1,%h2"
[(set_attr "type" "var_shift_rotate,shift")])
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
- (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
- "TARGET_POWER"
- "@
- sre. %3,%1,%2
- mr. %1,%1
- {s%A2i.|s%A2wi.} %3,%1,%h2
- #
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,4,8,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 3)
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
- "! TARGET_POWER && TARGET_32BIT"
+ "TARGET_32BIT"
"@
mr. %1,%1
{sr.|srw.} %3,%1,%2
(match_operand:SI 2 "reg_or_cint_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWER && TARGET_32BIT && reload_completed"
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 3)
(lshiftrt:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
- "TARGET_POWER"
- "@
- sre. %0,%1,%2
- mr. %0,%1
- {s%A2i.|s%A2wi.} %0,%1,%h2
- #
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,4,8,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && TARGET_32BIT"
+ "TARGET_32BIT"
"@
mr. %0,%1
{sr.|srw.} %0,%1,%2
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && TARGET_32BIT && reload_completed"
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(lshiftrt:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(const_int 0)))]
"")
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 1)
- (match_operand:SI 1 "gpc_reg_operand" "r"))
- (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 31)))]
- "TARGET_POWER"
- "rrib %0,%1,%2")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 1)
- (match_operand:SI 1 "gpc_reg_operand" "r"))
- (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 31)))]
- "TARGET_POWER"
- "rrib %0,%1,%2")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 1)
- (match_operand:SI 1 "gpc_reg_operand" "r"))
- (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 1)
- (const_int 0)))]
- "TARGET_POWER"
- "rrib %0,%1,%2")
-
-(define_expand "ashrsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" "")))]
- ""
- "
-{
- if (TARGET_POWER)
- emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_insn "ashrsi3_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
- (clobber (match_scratch:SI 3 "=q,X"))]
- "TARGET_POWER"
- "@
- srea %0,%1,%2
- {srai|srawi} %0,%1,%h2"
- [(set_attr "type" "shift")])
-
-(define_insn "ashrsi3_no_power"
+(define_insn "ashrsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
- "! TARGET_POWER"
+ ""
"@
{sra|sraw} %0,%1,%2
{srai|srawi} %0,%1,%h2"
(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))
- (clobber (match_scratch:SI 4 "=q,X,q,X"))]
- "TARGET_POWER"
+ (clobber (match_scratch:SI 3 "=r,r,r,r"))]
+ ""
"@
- srea. %3,%1,%2
+ {sra.|sraw.} %3,%1,%2
{srai.|srawi.} %3,%1,%h2
#
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(set_attr "length" "4,4,8,8")])
(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" ""))
(const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 3)
+ (clobber (match_scratch:SI 3 ""))]
+ "reload_completed"
+ [(set (match_dup 3)
(ashiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))]
- "! TARGET_POWER"
- "@
- {sra.|sraw.} %3,%1,%2
- {srai.|srawi.} %3,%1,%h2
- #
- #"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWER && reload_completed"
- [(set (match_dup 3)
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 "=q,X,q,X"))]
- "TARGET_POWER"
- "@
- srea. %0,%1,%2
- {srai.|srawi.} %0,%1,%h2
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER"
+ ""
"@
{sra.|sraw.} %0,%1,%2
{srai.|srawi.} %0,%1,%h2
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(ashiftrt:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
- "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
+ "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
&& !TARGET_SIMPLE_FPU"
"")
"fsqrts %0,%1"
[(set_attr "type" "ssqrt")])
-(define_insn ""
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
- "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
- "fsqrt %0,%1"
- [(set_attr "type" "dsqrt")])
-
(define_insn "*rsqrtsf_internal1"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
- "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_DOUBLE_FLOAT"
+ "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"")
(define_insn "*sqrtdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
- "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_DOUBLE_FLOAT
+ "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& !VECTOR_UNIT_VSX_P (DFmode)"
"fsqrt %0,%1"
[(set_attr "type" "dsqrt")])
(define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
- "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT
+ "TARGET_POWERPC && TARGET_HARD_FLOAT
&& ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
"
{
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
- "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_DOUBLE_FLOAT"
+ "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"#"
""
[(pc)]
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
UNSPEC_FCTIWZ))]
- "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_DOUBLE_FLOAT"
+ "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"{fcirz|fctiwz} %0,%1"
[(set_attr "type" "fp")])
"! TARGET_POWERPC64"
"
{
- if (! TARGET_POWER && ! TARGET_POWERPC)
+ if (! TARGET_POWERPC)
{
emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
}
DONE;
}
- else if (TARGET_POWER)
- {
- emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
}")
-(define_insn "mulsidi3_mq"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWER"
- "mul %0,%1,%2\;mfmq %L0"
- [(set_attr "type" "imul")
- (set_attr "length" "8")])
-
(define_insn "*mulsidi3_no_mq"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
+ "TARGET_POWERPC && ! TARGET_POWERPC64"
"*
{
return (WORDS_BIG_ENDIAN)
operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
}")
-(define_expand "umulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
- "TARGET_POWERPC && ! TARGET_POWERPC64"
- "
-{
- if (TARGET_POWER)
- {
- emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
-}")
-
-(define_insn "umulsidi3_mq"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWERPC && TARGET_POWER"
- "*
-{
- return (WORDS_BIG_ENDIAN)
- ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
- : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
-}"
- [(set_attr "type" "imul")
- (set_attr "length" "8")])
-
-(define_insn "*umulsidi3_no_mq"
+(define_insn "umulsidi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
+ "TARGET_POWERPC && ! TARGET_POWERPC64"
"*
{
return (WORDS_BIG_ENDIAN)
""
"
{
- if (! TARGET_POWER && ! TARGET_POWERPC)
+ if (! TARGET_POWERPC)
{
emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
DONE;
}
- else if (TARGET_POWER)
- {
- emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
}")
-(define_insn "smulsi3_highpart_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWER"
- "mul %0,%1,%2"
- [(set_attr "type" "imul")])
-
(define_insn "*smulsi3_highpart_no_mq"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(truncate:SI
(sign_extend:DI
(match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 32))))]
- "TARGET_POWERPC && ! TARGET_POWER"
+ "TARGET_POWERPC"
"mulhw %0,%1,%2"
[(set_attr "type" "imul")])
(match_operand:SI 2 "gpc_reg_operand" "")))
(const_int 32))))]
"TARGET_POWERPC"
- "
-{
- if (TARGET_POWER)
- {
- emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
-}")
-
-(define_insn "umulsi3_highpart_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWERPC && TARGET_POWER"
- "mulhwu %0,%1,%2"
- [(set_attr "type" "imul")])
+ "")
(define_insn "*umulsi3_highpart_no_mq"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:DI
(match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 32))))]
- "TARGET_POWERPC && ! TARGET_POWER"
+ "TARGET_POWERPC"
"mulhwu %0,%1,%2"
[(set_attr "type" "imul")])
-;; If operands 0 and 2 are in the same register, we have a problem. But
-;; operands 0 and 1 (the usual case) can be in the same register. That's
-;; why we have the strange constraints below.
-(define_insn "ashldi3_power"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
- (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
- (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
- (clobber (match_scratch:SI 3 "=X,q,q,q"))]
- "TARGET_POWER"
- "@
- {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
- sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
- sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
- sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
- [(set_attr "length" "8")])
-
-(define_insn "lshrdi3_power"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
- (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
- (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
- (clobber (match_scratch:SI 3 "=X,q,q,q"))]
- "TARGET_POWER"
- "@
- {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
- sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
- sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
- sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
- [(set_attr "length" "8")])
-
;; Shift by a variable amount is too complex to be worth open-coding. We
;; just handle shifts by constants.
-(define_insn "ashrdi3_power"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
- (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "M,i")))
- (clobber (match_scratch:SI 3 "=X,q"))]
- "TARGET_POWER"
- "@
- {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
- sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
- [(set_attr "type" "shift")
- (set_attr "length" "8")])
-
(define_insn "ashrdi3_no_power"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "M,i")))]
- "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
+ "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
"@
{srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
{sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" "")))]
- "TARGET_POWERPC64 || TARGET_POWER"
- "
-{
- if (TARGET_POWERPC64)
- ;
- else if (TARGET_POWER)
- {
- emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
- DONE;
- }
- else
- FAIL;
-}")
+ "TARGET_POWERPC64"
+ "")
(define_insn "*ashldi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" "")))]
- "TARGET_POWERPC64 || TARGET_POWER"
- "
-{
- if (TARGET_POWERPC64)
- ;
- else if (TARGET_POWER)
- {
- emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
- DONE;
- }
- else
- FAIL;
-}")
+ "TARGET_POWERPC64"
+ "")
(define_insn "*lshrdi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
{
if (TARGET_POWERPC64)
;
- else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
- {
- emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
- DONE;
- }
else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
&& WORDS_BIG_ENDIAN)
{
(define_expand "fix_trunctfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
- "!TARGET_IEEEQUAD
- && (TARGET_POWER2 || TARGET_POWERPC)
- && TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE)
- && TARGET_LONG_DOUBLE_128"
+ "!TARGET_IEEEQUAD && TARGET_POWERPC && TARGET_HARD_FLOAT
+ && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
{
if (TARGET_E500_DOUBLE)
emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
(clobber (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
- "!TARGET_IEEEQUAD
- && (TARGET_POWER2 || TARGET_POWERPC)
+ "!TARGET_IEEEQUAD && TARGET_POWERPC
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
{
operands[2] = gen_reg_rtx (DFmode);
}")
\f
;; TImode is similar, except that we usually want to compute the address into
-;; a register and use lsi/stsi (the exception is during reload). MQ is also
-;; clobbered in stsi for POWER, so we need a SCRATCH for it.
-
-;; We say that MQ is clobbered in the last alternative because the first
-;; alternative would never get used otherwise since it would need a reload
-;; while the 2nd alternative would not. We put memory cases first so they
-;; are preferred. Otherwise, we'd try to reload the output instead of
-;; giving the SCRATCH mq.
-
-(define_insn "*movti_power"
- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
- (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))
- (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
- "TARGET_POWER && ! TARGET_POWERPC64
- && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
- "*
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
-
- case 0:
- if (TARGET_STRING)
- return \"{stsi|stswi} %1,%P0,16\";
- case 1:
- return \"#\";
- case 2:
- /* If the address is not used in the output, we can use lsi. Otherwise,
- fall through to generating four loads. */
- if (TARGET_STRING
- && ! reg_overlap_mentioned_p (operands[0], operands[1]))
- return \"{lsi|lswi} %0,%P1,16\";
- /* ... fall through ... */
- case 3:
- case 4:
- case 5:
- return \"#\";
- }
-}"
- [(set_attr "type" "store,store,load,load,*,*")])
+;; a register and use lsi/stsi (the exception is during reload).
(define_insn "*movti_string"
[(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
(match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
- "! TARGET_POWER && ! TARGET_POWERPC64
+ "! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
{
(match_operand:SI 9 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
(match_operand:SI 10 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
"{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 8 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
(match_operand:SI 9 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
"{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 7 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
(match_operand:SI 8 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
"{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 6 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
(match_operand:SI 7 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
"{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 5 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
(match_operand:SI 6 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
"{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
(match_operand:SI 5 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
"{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
+\f
+(define_expand "setmemsi"
+ [(parallel [(set (match_operand:BLK 0 "" "")
+ (match_operand 2 "const_int_operand" ""))
+ (use (match_operand:SI 1 "" ""))
+ (use (match_operand:SI 3 "" ""))])]
+ ""
+ "
+{
+ /* If value to set is not zero, use the library routine. */
+ if (operands[2] != const0_rtx)
+ FAIL;
-(define_insn "*stmsi8_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
- (match_operand:SI 7 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
- (match_operand:SI 8 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
- (match_operand:SI 9 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
- (match_operand:SI 10 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi7_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
- (match_operand:SI 7 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
- (match_operand:SI 8 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
- (match_operand:SI 9 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi6_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
- (match_operand:SI 7 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
- (match_operand:SI 8 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi5_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
- (match_operand:SI 7 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi4_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi3_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-\f
-(define_expand "setmemsi"
- [(parallel [(set (match_operand:BLK 0 "" "")
- (match_operand 2 "const_int_operand" ""))
- (use (match_operand:SI 1 "" ""))
- (use (match_operand:SI 3 "" ""))])]
- ""
- "
-{
- /* If value to set is not zero, use the library routine. */
- if (operands[2] != const0_rtx)
- FAIL;
-
- if (expand_block_clear (operands))
- DONE;
- else
- FAIL;
-}")
+ if (expand_block_clear (operands))
+ DONE;
+ else
+ FAIL;
+}")
;; String/block move insn.
;; Argument 0 is the destination
"TARGET_STRING"
"")
-(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (reg:SI 9))
- (clobber (reg:SI 10))
- (clobber (reg:SI 11))
- (clobber (reg:SI 12))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER
- && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
- || INTVAL (operands[2]) == 0)
- && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
- && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
- && REGNO (operands[4]) == 5"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
(define_insn ""
[(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
(clobber (reg:SI 11))
(clobber (reg:SI 12))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER
+ "TARGET_STRING
&& ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
|| INTVAL (operands[2]) == 0)
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
"TARGET_STRING"
"")
-(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (reg:SI 9))
- (clobber (reg:SI 10))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER
- && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
- && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
- && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
- && REGNO (operands[4]) == 5"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
(define_insn ""
[(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
(clobber (reg:SI 9))
(clobber (reg:SI 10))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER
+ "TARGET_STRING
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
"TARGET_STRING"
"")
-(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER
- && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
- && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
- && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
- && REGNO (operands[4]) == 5"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
(define_insn ""
[(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
(clobber (reg:SI 7))
(clobber (reg:SI 8))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER
+ "TARGET_STRING
&& INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
"TARGET_STRING && ! TARGET_POWERPC64"
"")
-(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_scratch:DI 4 "=&r"))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
- && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
(define_insn ""
[(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_scratch:DI 4 "=&r"))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
+ "TARGET_STRING && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "store_ux")
"TARGET_STRING"
"")
-(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_scratch:SI 4 "=&r"))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER
- && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
(define_insn ""
[(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_scratch:SI 4 "=&r"))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER
- && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
+ "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")
stfdu %3,%2(%0)"
[(set_attr "type" "fpstore_ux,fpstore_u")])
-;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
-
-(define_insn "*lfq_power2"
- [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
- (match_operand:V2DF 1 "memory_operand" ""))]
- "TARGET_POWER2
- && TARGET_HARD_FLOAT && TARGET_FPRS"
- "lfq%U1%X1 %0,%1")
-
-(define_peephole2
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (match_operand:DF 1 "memory_operand" ""))
- (set (match_operand:DF 2 "gpc_reg_operand" "")
- (match_operand:DF 3 "memory_operand" ""))]
- "TARGET_POWER2
- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && registers_ok_for_quad_peep (operands[0], operands[2])
- && mems_ok_for_quad_peep (operands[1], operands[3])"
- [(set (match_dup 0)
- (match_dup 1))]
- "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
- operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
-
-(define_insn "*stfq_power2"
- [(set (match_operand:V2DF 0 "memory_operand" "")
- (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
- "TARGET_POWER2
- && TARGET_HARD_FLOAT && TARGET_FPRS"
- "stfq%U0%X0 %1,%0")
-
-
-(define_peephole2
- [(set (match_operand:DF 0 "memory_operand" "")
- (match_operand:DF 1 "gpc_reg_operand" ""))
- (set (match_operand:DF 2 "memory_operand" "")
- (match_operand:DF 3 "gpc_reg_operand" ""))]
- "TARGET_POWER2
- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && registers_ok_for_quad_peep (operands[1], operands[3])
- && mems_ok_for_quad_peep (operands[0], operands[2])"
- [(set (match_dup 0)
- (match_dup 1))]
- "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
- operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
;; After inserting conditional returns we can sometimes have
;; unnecessary register moves. Unfortunately we cannot have a
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
- "!TARGET_POWER"
+ ""
"#"
- "!TARGET_POWER"
+ ""
[(set (match_dup 0)
(clz:GPR (match_dup 3)))
(set (match_dup 0)
(const_int 0)))
(set (match_operand:P 0 "gpc_reg_operand" "=r")
(eq:P (match_dup 1) (match_dup 2)))]
- "!TARGET_POWER && optimize_size"
+ "optimize_size"
"#"
- "!TARGET_POWER && optimize_size"
+ "optimize_size"
[(set (match_dup 0)
(clz:P (match_dup 4)))
(parallel [(set (match_dup 3)
operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
})
-(define_insn "*eqsi_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
- (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
- (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
- "TARGET_POWER"
- "@
- xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
- {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
- {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
- {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
- {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
- [(set_attr "type" "three,two,three,three,three")
- (set_attr "length" "12,8,12,12,12")])
-
;; We have insns of the form shown by the first define_insn below. If
;; there is something inside the comparison operation, we must split it.
(define_split
(lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
(const_int 31)))
(clobber (match_scratch:SI 2 "=&r"))]
- "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
+ "TARGET_32BIT && !TARGET_ISEL"
"{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
[(set_attr "type" "two")
(set_attr "length" "8")])
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O")))
- (clobber (match_scratch:SI 3 "=r,X"))]
- "TARGET_POWER"
- "@
- doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
- {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC
- (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (le:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 3 "=r,X,r,X"))]
- "TARGET_POWER"
- "@
- doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
- {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
- #
- #"
- [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
- (set_attr "length" "12,12,16,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (le:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (le:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
- {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
- "TARGET_POWER"
- "@
- doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
- {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
- #
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,12,16,16")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 4)
- (plus:SI (le:SI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
- (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
- {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
- #
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,12,16,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
- {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
- [(set_attr "length" "12")])
-
(define_insn "*leu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(leu:P (match_operand:P 1 "gpc_reg_operand" "r")
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI")))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (lt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER"
- "@
- doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (lt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (lt:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r")))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 4 "=&r,&r"))]
- "TARGET_POWER"
- "@
- doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 4)
- (plus:SI (lt:SI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER"
- "@
- doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
- [(set_attr "length" "12")])
-
(define_insn_and_split "*ltu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
[(set_attr "type" "two")
(set_attr "length" "8")])
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI")))
- (clobber (match_scratch:SI 3 "=r"))]
- "TARGET_POWER"
- "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ge:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_POWER"
- "@
- doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ge:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (ge:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r")))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 4 "=&r,&r"))]
- "TARGET_POWER"
- "@
- doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 4)
- (plus:SI (ge:SI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER"
- "@
- doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
- [(set_attr "length" "12")])
-
(define_insn "*geu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "r")))]
- "TARGET_POWER"
- "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (gt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (gt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (gt:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_insn "*plus_gt0<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=&r")
(plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "r"))
- (match_operand:SI 3 "gpc_reg_operand" "r")))]
- "TARGET_POWER"
- "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,r"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 4 "=&r,&r"))]
- "TARGET_POWER"
- "@
- doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 4)
- (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,r"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "r"))))]
- "TARGET_POWER"
- "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
- [(set_attr "length" "12")])
-
(define_insn_and_split "*gtu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
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