* mips-opc.c (CP): New macro.

	(mips_builtin_opcodes): Mark c0, c2 and c3 as CP.  Add Octeon to the
	membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0.  Add dmfc2 and
	dmtc2 Octeon instructions.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ab435f5..762c724 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2008-07-07  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * mips-opc.c (CP): New macro.
+       (mips_builtin_opcodes): Mark c0, c2 and c3 as CP.  Add Octeon to the
+       membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0.  Add dmfc2 and
+       dmtc2 Octeon instructions.
+
 2008-07-07  Stan Shebs  <stan@codesourcery.com>
 
        * dis-init.c (init_disassemble_info): Init endian_code field.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 75503fa..82a01f8 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -62,6 +62,7 @@
 #define WR_C1  INSN_COP
 #define WR_C2   INSN_COP
 #define WR_C3   INSN_COP
+#define CP     INSN_COP
 
 #define WR_HI  INSN_WRITE_HI
 #define RD_HI  INSN_READ_HI
@@ -577,8 +578,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3      },
 {"ddivu",   "d,v,t",   0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3      },
 {"ddivu",   "d,v,I",   0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3      },
-{"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
-{"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
+{"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33|IOCT},
+{"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33|IOCT},
 {"dins",    "t,r,I,+I",        0,    (int) M_DINS,     INSN_MACRO,             0,              I65     },
 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,                    0,              I65     },
 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,                    0,              I65     },
@@ -613,14 +614,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmaccu",  "d,s,t",   0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
 {"dmaccus", "d,s,t",   0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,             N411    },
-{"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3      },
-{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64     },
-{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64     },
+{"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3|IOCT },
+{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64|IOCT},
+{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64|IOCT},
 {"dmt",     "",                0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
 {"dmt",     "t",       0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
-{"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
-{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64     },
-{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64     },
+{"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3|IOCT },
+{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64|IOCT},
+{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64|IOCT},
 {"dmfc1",   "t,S",     0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,             I3      },
 {"dmtc1",   "t,S",     0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
@@ -692,8 +693,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
 {"dvpe",    "",                0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
 {"dvpe",    "t",       0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
-{"ei",      "",                0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
-{"ei",      "t",       0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
+{"ei",      "",                0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33|IOCT},
+{"ei",      "t",       0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33|IOCT},
 {"emt",     "",                0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
 {"emt",     "t",       0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
 {"eret",    "",         0x42000018, 0xffffffff, 0,                     0,              I3_32   },
@@ -864,9 +865,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mftlo",   "d",       0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
 {"mftlo",   "d,*",     0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,            0,              MT32    },
-{"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
-{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32     },
-{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32     },
+{"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1|IOCT },
+{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32|IOCT},
+{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32|IOCT},
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
 {"mfc1",    "t,G",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
 {"mfhc1",   "t,S",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
@@ -939,9 +940,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msubu",   "7,s,t",   0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
 {"mtpc",    "t,P",     0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
 {"mtps",    "t,P",     0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
-{"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
-{"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32     },
-{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32     },
+{"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1|IOCT },
+{"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32|IOCT},
+{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32|IOCT},
 {"mtc1",    "t,S",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
 {"mtc1",    "t,G",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
 {"mthc1",   "t,S",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
@@ -1491,8 +1492,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ctc2",    "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
 {"dmfc2",   "t,G",     0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
 {"dmfc2",   "t,G,H",   0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
+{"dmfc2",   "t,i",     0x48200000, 0xffe00000, LCD|WR_t|RD_C2,         0,              IOCT    },
 {"dmtc2",   "t,G",     0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
 {"dmtc2",   "t,G,H",   0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
+{"dmtc2",   "t,i",     0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              IOCT    },
 {"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
 {"mfc2",    "t,G,H",   0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
 {"mfhc2",   "t,G",     0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },
@@ -1958,10 +1961,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
    disassembler recognizes more specific versions first.  */
-{"c0",      "C",       0x42000000, 0xfe000000, 0,                      0,              I1      },
+{"c0",      "C",       0x42000000, 0xfe000000, CP,                     0,              I1      },
 {"c1",      "C",       0x46000000, 0xfe000000, FP_S,                   0,              I1      },
-{"c2",      "C",       0x4a000000, 0xfe000000, 0,                      0,              I1      },
-{"c3",      "C",       0x4e000000, 0xfe000000, 0,                      0,              I1      },
+{"c2",      "C",       0x4a000000, 0xfe000000, CP,                     0,              I1      },
+{"c3",      "C",       0x4e000000, 0xfe000000, CP,                     0,              I1      },
 {"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
 {"cop1",     "C",      0,    (int) M_COP1,     INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },