[AMDGPU] SDWA: remove omod src operand for VOP2b instructions

Summary: VOP2b instructions (v_subbrev_u32, v_add_i32 ...) shouldn't support OMod operand in SDWA encoding

Reviewers: rampitec, dp

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D40172

llvm-svn: 318761

diff --git a/llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt b/llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
index c697ebc..28a318b 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
@@ -354,6 +354,24 @@
 # GFX9: v_ldexp_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x66,0x02,0x06,0x05,0x02]
 0xf9 0x06 0x02 0x66 0x02 0x06 0x05 0x02
 
+# GFX9: v_add_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x32,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x32 0x02 0x06 0x05 0x02
+
+# GFX9: v_sub_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x34,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x34 0x02 0x06 0x05 0x02
+
+# GFX9: v_subrev_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x36,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x36 0x02 0x06 0x05 0x02
+
+# GFX9: v_addc_co_u32_sdwa v1, vcc, v2, v3, vcc  dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x38,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x38 0x02 0x06 0x05 0x02
+
+# GFX9: v_subb_co_u32_sdwa v1, vcc, v2, v3, vcc  dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3a,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x3a 0x02 0x06 0x05 0x02
+
+# GFX9: v_subbrev_co_u32_sdwa v1, vcc, v2, v3, vcc  dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3c,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x3c 0x02 0x06 0x05 0x02
+
 #-----------------------------------------------------------------------------#
 # VOPC
 #-----------------------------------------------------------------------------#

diff --git a/llvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt
index 4d9748d..c906ca5 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt
@@ -348,3 +348,20 @@
 # VI: v_ldexp_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x66,0x02,0x06,0x05,0x02]
 0xf9 0x06 0x02 0x66 0x02 0x06 0x05 0x02
 
+# VI: v_add_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x32,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x32 0x02 0x06 0x05 0x02
+
+# VI: v_sub_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x34,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x34 0x02 0x06 0x05 0x02
+
+# VI: v_subrev_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x36,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x36 0x02 0x06 0x05 0x02
+
+# VI: v_addc_u32_sdwa v1, vcc, v2, v3, vcc  dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x38,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x38 0x02 0x06 0x05 0x02
+
+# VI: v_subb_u32_sdwa v1, vcc, v2, v3, vcc  dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3a,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x3a 0x02 0x06 0x05 0x02
+
+# VI: v_subbrev_u32_sdwa v1, vcc, v2, v3, vcc  dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3c,0x02,0x06,0x05,0x02]
+0xf9 0x06 0x02 0x3c 0x02 0x06 0x05 0x02