+2013-05-15 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.c (iy86_option_override_internal): Update
+ processor_alias_table for missing PTA_PRFCHW and PTA_FXSR flags. Add
+ PTA_POPCNT to corei7 entry and remove PTA_SSE from athlon-4 entry.
+ Do not enable SSE prefetch on non-SSE 3dNow! targets. Enable
+ TARGET_PRFCHW for TARGET_3DNOW targets.
+ * config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW instead
+ of TARGET_3DNOW.
+ (*prefetch_3dnow): Enable for TARGET_PRFCHW only.
+
2013-05-15 Andreas Schwab <schwab@suse.de>
* config/m68k/m68k.md (*rotlhi3_lowpart, *rotlqi3_lowpart): Name
PR lto/57038
PR lto/47375
- * lto-symtab.c (lto_symtab_symbol_p): Add external symbol; weakrefs are
- not external.
- (lto_symtab_merge_decls): Fix thinko when dealing with non-lto_symtab decls.
+ * lto-symtab.c (lto_symtab_symbol_p): Add external symbol;
+ weakrefs are not external.
+ (lto_symtab_merge_decls): Fix thinko when dealing with
+ non-lto_symtab decls.
(lto_symtab_merge_cgraph_nodes): Use lto_symtab_symbol_p.
(lto_symtab_prevailing_decl): Get int sync with lto_symtab_symbol_p.
* varpool.c (dump_varpool_node): Dump more flags.
2013-05-14 Joern Rennecke <joern.rennecke@embecosm.com>
* config/avr/avr.c (avr_encode_section_info): Bail out if the type
- is error_mark_node.
+ is error_mark_node.
2013-05-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR target/56975
* config/i386/cygming.h (TARGET_PECOFF): Define as true.
- * config/i386/i386.h (TARGET_PECOFF): Define by default
- as false.
+ * config/i386/i386.h (TARGET_PECOFF): Define by default as false.
(PIC_OFFSET_TABLE_REGNUM): Use TARGET_PECOFF.
- * config/i386/i386.c (ix86_option_override_internal):
- Likewise.
+ * config/i386/i386.c (ix86_option_override_internal): Likewise.
(ix86_expand_prologue): Likewise.
(ix86_expand_split_stack_prologue): Likewise.
(legitimate_pic_address_disp_p): Likewise.
* mode-switching.c (optimize_mode_switching): Set correct RTL profile.
* config/i386/i386.c (ix86_compute_frame_layout,
- ix86_expand_epilogue, emit_i387_cw_initialization, ix86_expand_vector_move_misalign,
- ix86_fp_comparison_strategy, ix86_local_alignment): Fix use of size/speed predicates.
+ ix86_expand_epilogue, emit_i387_cw_initialization,
+ ix86_expand_vector_move_misalign, ix86_fp_comparison_strategy,
+ ix86_local_alignment): Fix use of size/speed predicates.
2013-05-13 Jakub Jelinek <jakub@redhat.com>
2013-05-13 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
- * config/i386/i386.c (processor_target_table): Modified default
+ * config/i386/i386.c (processor_target_table): Modified default
alignment values for AMD BD and BT architectures.
2013-05-13 Marc Glisse <marc.glisse@inria.fr>
{"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
{"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
{"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
- {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
+ {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
+ {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
+ {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+ PTA_MMX | PTA_SSE | PTA_FXSR},
{"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
{"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
{"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_CX16 | PTA_FXSR},
{"corei7", PROCESSOR_COREI7, CPU_COREI7,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
+ | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
{"corei7-avx", PROCESSOR_COREI7, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
{"geode", PROCESSOR_GEODE, CPU_GEODE,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
{"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
- {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
- {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+ {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
+ {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
{"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
{"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
{"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR},
{"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR},
{"x86-64", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
{"k8", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"k8-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"opteron", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"opteron-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"athlon64", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"athlon64-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"athlon-fx", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
+ PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+ | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
{"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
+ PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+ | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
{"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
/* Enable SSE prefetch. */
- if (TARGET_SSE || TARGET_PRFCHW)
+ if (TARGET_SSE || (TARGET_PRFCHW && !TARGET_3DNOW))
x86_prefetch_sse = true;
- /* Turn on popcnt instruction for -msse4.2 or -mabm. */
+ /* Enable prefetch{,w} instructions for -m3dnow. */
+ if (TARGET_3DNOW)
+ ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW & ~ix86_isa_flags_explicit;
+
+ /* Enable popcnt instruction for -msse4.2 or -mabm. */
if (TARGET_SSE4_2 || TARGET_ABM)
ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
- /* Turn on lzcnt instruction for -mabm. */
+ /* Enable lzcnt instruction for -mabm. */
if (TARGET_ABM)
ix86_isa_flags |= OPTION_MASK_ISA_LZCNT & ~ix86_isa_flags_explicit;